2009 Microchip Technology Inc.
DS39761C-page 303
PIC18F2682/2685/4682/4685
REGISTER 23-34: BnDLC: TX/RX BUFFER n DATA LENGTH CODE REGISTERS IN RECEIVE MODE
[0
≤ n ≤ 5, TXnEN (BSEL<n>) = 0](1)
U-0
R-x
—
RXRTR
RB1
RB0
DLC3
DLC2
DLC1
DLC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6
RXRTR: Receiver Remote Transmission Request bit
1 = This is a remote transmission request
0 = This is not a remote transmission request
bit 5
RB1: Reserved bit 1
Reserved by CAN Spec and read as ‘0’.
bit 4
RB0: Reserved bit 0
Reserved by CAN Spec and read as ‘0’.
bit 3-0
DLC3:DLC0: Data Length Code bits
1111 = Reserved
1110 = Reserved
1101 = Reserved
1100 = Reserved
1011 = Reserved
1010 = Reserved
1001 = Reserved
1000 = Data length = 8 bytes
0111 = Data length = 7 bytes
0110 = Data length = 6 bytes
0101 = Data length = 5 bytes
0100 = Data length = 4 bytes
0011 = Data length = 3 bytes
0010 = Data length = 2 bytes
0001 = Data length = 1 bytes
0000 = Data length = 0 bytes
Note 1:
These registers are available in Mode 1 and 2 only.
