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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� PIC18F4455-I/P
寤犲晢锛� Microchip Technology
鏂囦欢闋佹暩(sh霉)锛� 178/438闋�
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鎻忚堪锛� IC PIC MCU FLASH 12KX16 40DIP
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鏍稿績铏曠悊鍣細 PIC
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鐢�(ch菐n)鍝佺洰閷勯爜闈細 646 (CN2011-ZH PDF)
閰嶇敤锛� I3-DB18F4550-ND - BOARD DAUGHTER ICEPIC3
DM163025-ND - PIC DEM FULL SPEED USB DEMO BRD
DVA18XP400-ND - DEVICE ADAPTER 18F4220 PDIP 40LD
444-1001-ND - DEMO BOARD FOR PICMICRO MCU
ACICE0206-ND - ADAPTER MPLABICE 40P 600 MIL
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2011-2012 Microchip Technology Inc.
Preliminary
DS41575B-page 257
PIC16(L)F1933
24.6.5
I2C MASTER MODE REPEATED
START CONDITION TIMING
A Repeated Start condition (Figure 24-27) occurs when
the RSEN bit of the SSPCON2 register is programmed
high and the master state machine is no longer active.
When the RSEN bit is set, the SCL pin is asserted low.
When the SCL pin is sampled low, the Baud Rate
Generator is loaded and begins counting. The SDA pin
is released (brought high) for one Baud Rate Generator
count (TBRG). When the Baud Rate Generator times
out, if SDA is sampled high, the SCL pin will be
deasserted (brought high). When SCL is sampled high,
the Baud Rate Generator is reloaded and begins count-
ing. SDA and SCL must be sampled high for one TBRG.
This action is then followed by assertion of the SDA pin
(SDA = 0) for one TBRG while SCL is high. SCL is
asserted low. Following this, the RSEN bit of the
SSPCON2 register will be automatically cleared and
the Baud Rate Generator will not be reloaded, leaving
the SDA pin held low. As soon as a Start condition is
detected on the SDA and SCL pins, the S bit of the
SSPSTAT register will be set. The SSPIF bit will not be
set until the Baud Rate Generator has timed out.
FIGURE 24-27:
REPEAT START CONDITION WAVEFORM
Note 1:
If RSEN is programmed while any other
event is in progress, it will not take effect.
2:
A bus collision during the Repeated Start
condition occurs if:
SDA is sampled low when SCL
goes from low-to-high.
SCL goes low before SDA is
asserted low. This may indicate
that another master is attempting to
transmit a data 鈥�1鈥�.
SDA
SCL
Repeated Start
Write to SSPCON2
Write to SSPBUF occurs here
At completion of Start bit,
hardware clears RSEN bit
1st bit
S bit set by hardware
TBRG
SDA = 1,
SCL (no change)
SCL = 1
occurs here
TBRG
and sets SSPIF
Sr
鐩搁棞(gu膩n)PDF璩囨枡
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