IPD Power-down Current
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� PIC18F4410-I/P
寤犲晢锛� Microchip Technology
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 89/234闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC MCU FLASH 8KX16 40DIP
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 10
绯诲垪锛� PIC® 18F
鏍稿績铏曠悊鍣細 PIC
鑺珨灏哄锛� 8-浣�
閫熷害锛� 40MHz
閫ｉ€氭€э細 I²C锛孲PI锛孶ART/USART
澶栧湇瑷�(sh猫)鍌欙細 娆犲妾㈡脯(c猫)/寰�(f霉)浣�锛孒LVD锛孭OR锛孭WM锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 36
绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 16KB锛�8K x 16锛�
绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 闁冨瓨
RAM 瀹归噺锛� 768 x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 4.2 V ~ 5.5 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 13x10b
鎸暕鍣ㄥ瀷锛� 鍏�(n猫i)閮�
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 40-DIP锛�0.600"锛�15.24mm锛�
鍖呰锛� 绠′欢
閰嶇敤锛� DVA18XP400-ND - DEVICE ADAPTER 18F4220 PDIP 40LD
444-1001-ND - DEMO BOARD FOR PICMICRO MCU
ACICE0206-ND - ADAPTER MPLABICE 40P 600 MIL
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2003 Microchip Technology Inc.
DS39582B-page 177
PIC16F87XA
IPD
Power-down Current(3,5)
D020
16LF87XA
鈥�
7.5
30
AVDD = 3.0V, WDT enabled,
-40
掳C to +85掳C
D020
16F87XA
鈥�
10.5
42
60
A
VDD = 4.0V, WDT enabled,
-40
掳C to +85掳C
VDD = 4.0V, WDT enabled,
-40
掳C to +125掳C (extended)
D021
16LF87XA
鈥�
0.9
5
AVDD = 3.0V, WDT disabled,
0
掳C to +70掳C
D021
16F87XA
鈥�
1.5
16
20
A
VDD = 4.0V, WDT disabled,
-40
掳C to +85掳C
VDD = 4.0V, WDT disabled,
-40
掳C to +125掳C (extended)
D021A
16LF87XA
0.9
5
AVDD = 3.0V, WDT disabled,
-40
掳C to +85掳C
D021A
16F87XA
1.5
19
A
VDD = 4.0V, WDT disabled,
-40
掳C to +85掳C
D023
IBOR
Brown-out
Reset Current(6)
鈥�
85
200
A
BOR enabled, VDD = 5.0V
17.1
DC Characteristics:
PIC16F873A/874A/876A/877A (Industrial, Extended)
PIC16LF873A/874A/876A/877A (Industrial) (Continued)
PIC16LF873A/874A/ 876A/877A
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40掳C
鈮� TA 鈮� +85掳C for industrial
PIC16F873A/874A/876A/877A
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40掳C
鈮� TA 鈮� +85掳C for industrial
-40掳C
鈮� TA 鈮� +125掳C for extended
Param
No.
Symbol
Characteristic/
Device
Min
Typ
Max
Units
Conditions
Legend: Rows with standard voltage device data only are shaded for improved readability.
Data in 鈥淭yp鈥� column is at 5V, 25掳C, unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1:
This is the limit to which VDD can be lowered without losing RAM data.
2:
The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading, switching rate, oscillator type, internal code execution pattern and temperature, also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3:
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD and VSS.
4:
For RC osc configuration, current through REXT is not included. The current through the resistor can be
estimated by the formula Ir = VDD/2REXT (mA) with REXT in k
.
5:
Timer1 oscillator (when enabled) adds approximately 20
A to the specification. This value is from
characterization and is for design guidance only. This is not tested.
6:
The
current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
7:
When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
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