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      2003 Microchip Technology Inc.
      DS39582B-page 227
      PIC16F87XA
      I2C Master Mode (Reception, 7-bit Address) ........... 103
      I2C Master Mode (Transmission,
      I2C Slave Mode (Transmission, 10-bit Address) ........ 89
      I2C Slave Mode (Transmission, 7-bit Address) .......... 87
      I2C Slave Mode with SEN = 1 (Reception,
      I2C Slave Mode with SEN = 0 (Reception,
      I2C Slave Mode with SEN = 0 (Reception,
      I2C Slave Mode with SEN = 1 (Reception,
      Parallel Slave Port (PIC16F874A/877A Only) .......... 187
      Parallel Slave Port (PSP) Read ................................. 52
      Parallel Slave Port (PSP) Write ................................. 52
      Reset, Watchdog Timer, Start-up Timer
      Slave Mode General Call Address Sequence
      (7 or 10-bit Address Mode) ................................ 94
      Slow Rise Time (MCLR Tied to VDD via
      SPI Master Mode (CKE = 0, SMP = 0) .................... 188
      SPI Master Mode (CKE = 1, SMP = 1) .................... 188
      SPI Mode (Slave Mode with CKE = 0) ....................... 78
      SPI Mode (Slave Mode with CKE = 1) ....................... 78
      Stop Condition Receive or Transmit Mode .............. 104
      Synchronous Reception
      Synchronous Transmission (Through TXEN) .......... 122
      Time-out Sequence on Power-up
      (MCLR Not Tied to VDD)
      Time-out Sequence on Power-up (MCLR Tied
      Timer0 and Timer1 External Clock .......................... 185
      USART Synchronous Receive
      USART Synchronous Transmission
      Wake-up from Sleep via Interrupt ............................ 157
      U
      Address Detect Enable (ADDEN Bit) ....................... 112
      Asynchronous Receive (9-bit Mode) ........................ 119
      See Asynchronous Receive (9-bit Mode).
      Baud Rate Generator (BRG) ................................... 113
      Baud Rates, Asynchronous Mode
      Baud Rates, Asynchronous Mode
      High Baud Rate Select (BRGH Bit) ................. 111
      Clock Source Select (CSRC Bit) .............................. 111
      Continuous Receive Enable (CREN Bit) .................. 112
      Receive Data, 9th Bit (RX9D Bit) ............................. 112
      Receive Enable, 9-bit (RX9 Bit) ............................... 112
      Serial Port Enable (SPEN Bit) ..........................111, 112
      Single Receive Enable (SREN Bit) .......................... 112
      Synchronous Master Reception ............................... 123
      Synchronous Master Transmission ......................... 121
      Synchronous Slave Reception ................................. 125
      Synchronous Slave Transmit ................................... 124
      Transmit Data, 9th Bit (TX9D) ................................. 111
      Transmit Enable (TXEN Bit) .................................... 111
      Transmit Enable, 9-bit (TX9 Bit) .............................. 111
      Transmit Shift Register Status (TRMT Bit) .............. 111
      USART Synchronous Receive Requirements ................. 193
      V
      Voltage Reference Specifications .................................... 180
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