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222
XMEGA A [MANUAL]
8077I鈥揂VR鈥�11/2012
19.10.4 ADDR
鈥� Address register
The TWI slave address register should be loaded with the 7-bit slave address (in the seven most significant bits of
ADDR) to which the TWI will respond. The lsb of ADDR is used to enable recognition of the general call address (0x00).
Bit 7:1
鈥� ADDR[7:1]: TWI Slave Address
This register contains the TWI slave address used by the slave address match logic to determine if a master has
addressed the slave. The seven most-significant bits (ADDR[7:1]) represent the slave address.
When using 10-bit addressing, the address match logic only supports hardware address recognition of the first byte of a
10-bit address. By setting ADDR[7:1] = 0b11110nn, 鈥漬n鈥� represents bits 9 and 8 of the slave address. The next byte
received is bits 7 to 0 in the 10-bit address, and this must be handled by software.
When the address match logic detects that a valid address byte is received, APIF is set and the DIR flag is updated.
If the PMEN bit in CTRLA is set, the address match logic responds to all addresses transmitted on the TWI bus. The
ADDR register is not used in this mode.
Bit 0
鈥� ADDR: General Call Recognition Enable
When ADDR[0] is set, this enables general call address recognition logic so the device can respond to a general address
call that addresses all devices on the bus.
19.10.5 DATA
鈥� Data register
The data (DATA) register is used when transmitting and received data. During data transfer, data are shifted from/to the
DATA register and to/from the bus. This implies that the DATA register cannot be accessed during byte transfers, and
this is prevented by hardware. The DATA register can be accessed only when the SCL line is held low by the slave; i.e.,
when CLKHOLD is set.
When a master is reading data from the slave, data to send must be written to the DATA register. The byte transfer is
started when the master starts to clock the data byte from the slave, followed by the slave receiving the acknowledge bit
from the master. DIF and CLKHOLD are set.
When a master writes data to the slave, DIF and CLKHOLD are set when one byte has been received in the DATA
register. If smart mode is enabled, reading the DATA register will trigger the bus operation as set by the ACKACT bit.
Accessing the DATA register will clear the slave interrupt flags and CLKHOLD. When an address match occurs, the
received address will be stored in the DATA register.
Bit
7
65
43
21
0
+0x03
ADDR[7:1]
ADDR[0]
Read/Write
R/W
Initial Value
0
Bit
7
6
543
210
+0x04
DATA[7:0]
Read/Write
R/W
Initial Value
0
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