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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | PIC18F2450-I/ML |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋佹暩(sh霉)锛� | 131/241闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC PIC MCU FLASH 8KX16 28QFN |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Asynchronous Stimulus 8-bit PIC® Microcontroller Portfolio |
| 妯欐簴鍖呰锛� | 61 |
| 绯诲垪锛� | PIC® 18F |
| 鏍稿績铏曠悊鍣細 | PIC |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 48MHz |
| 閫ｉ€氭€э細 | UART/USART锛孶SB |
| 澶栧湇瑷�(sh猫)鍌欙細 | 娆犲妾㈡脯/寰�(f霉)浣�锛孒LVD锛孭OR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 23 |
| 绋嬪簭瀛樺劜鍣ㄥ閲忥細 | 16KB锛�8K x 16锛� |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | 闁冨瓨 |
| RAM 瀹归噺锛� | 768 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 4.2 V ~ 5.5 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 10x10b |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 28-VQFN 瑁搁湶鐒婄洡 |
| 鍖呰锛� | 绠′欢 |
| 鐢�(ch菐n)鍝佺洰閷勯爜闈細 | 646 (CN2011-ZH PDF) |
| 閰嶇敤锛� | AC164322-ND - MODULE SOCKET MPLAB PM3 28/44QFN DM163025-ND - PIC DEM FULL SPEED USB DEMO BRD |
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216
XMEGA A [MANUAL]
8077I鈥揂VR鈥�11/2012
Bits 7:3
鈥� Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
Bit 2
鈥� ACKACT: Acknowledge Action
This bit defines the master's acknowledge behavior in master read mode. The acknowledge action is executed when a
command is written to the CMD bits. If SMEN in the CTRLB register is set, the acknowledge action is performed when
the DATA register is read.
Table 19-4 lists the acknowledge actions.
Table 19-4. ACKACT bit description.
Bit 1:0
鈥� CMD[1:0]: Command
Writing the command (CMD) bits triggers a master operation as defined by Table 19-5 on page 216. The CMD bits are
strobe bits, and always read as zero. The acknowledge action is only valid in master read mode (R). In master write
mode (W), a command will only result in a repeated START or STOP condition. The ACKACT bit and the CMD bits can
be written at the same time, and then the acknowledge action will be updated before the command is triggered.
Table 19-5. CMD bits description.
Writing a command to the CMD bits will clear the master interrupt flags and the CLKHOLD flag.
19.9.4 STATUS 鈥� Status register
Bit 7
鈥� RIF: Read Interrupt Flag
This flag is set when a byte is successfully received in master read mode; i.e., no arbitration was lost or bus error
occurred during the operation. Writing a one to this bit location will clear RIF. When this flag is set, the master forces the
SCL line low, stretching the TWI clock period. Clearing the interrupt flags will release the SCL line.
This flag is also cleared automatically when:
Writing to the ADDR register
Writing to the DATA register
ACKACT
Action
0
Send ACK
1
Send NACK
CMD[1:0]
Group Configuration
MODE
Operation
00
NOACT
X
Reserved
01
START
X
Execute acknowledge action succeeded by repeated START condition
10
BYTEREC
W
No operation
R
Execute acknowledge action succeeded by a byte receive
11
STOP
X
Execute acknowledge action succeeded by issuing a STOP condition
Bit
76543210
+0x03
RIF
WIF
CLKHOLD
RXACK
ARBLOST
BUSERR
BUSSTATE[1:0]
Read/Write
R/W
R
R/W
Initial Value
00000000
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