
PIC18F1230/1330
DS39758D-page 112
2009 Microchip Technology Inc.
13.1
Timer1 Operation
Timer1 can operate in one of these modes:
As a timer
As a synchronous counter
As an asynchronous counter
The operating mode is determined by the Clock Select
bit, TMR1CS (T1CON<1>).
When TMR1CS = 0, Timer1 increments every
instruction cycle. When TMR1CS = 1, Timer1
increments on every rising edge of the external clock
input or the Timer1 oscillator, if enabled.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the T1OSI and T1OSO/T1CKI pins become
inputs. That is, the corresponding TRISA bit value is
ignored, and the pins are read as ‘0’.
FIGURE 13-1:
TIMER1 BLOCK DIAGRAM
FIGURE 13-2:
TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE
T1OSC
TMR1H
TMR1L
T1SYNC
TMR1CS
T1CKPS1:T1CKPS0
Peripheral Clocks
FOSC/4
Internal
Clock
TMR1ON
On/Off
Synchronize
det
1
0
1
Synchronized
Clock Input
2
TMR1IF
Overflow
TMR1
T1OSCEN
Enable
Oscillator(1)
Interrupt
Flag Bit
Note 1:
When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
T1OSI
T1OSO/T1CKI
Prescaler
1, 2, 4, 8
Timer1
TMR1L
T1OSC
T1SYNC
TMR1CS
T1CKPS1:T1CKPS0
Peripheral Clocks
T1OSCEN
Enable
Oscillator(1)
TMR1IF
Overflow
Interrupt
FOSC/4
Internal
Clock
TMR1ON
On/Off
Prescaler
1, 2, 4, 8
Synchronize
det
1
0
1
Synchronized
Clock Input
2
T1OSO/T1CKI
T1OSI
TMR1
Flag bit
Note 1:
When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
High Byte
Data Bus<7:0>
8
TMR1H
8
Read TMR1L
Write TMR1L