2001 Microchip Technology Inc.
DS39026C-page 67
PIC18CXX2
REGISTER 7-3:
INTCON3 REGISTER
R/W-1
U-0
R/W-0
U-0
R/W-0
INT2IP
INT1IP
—
INT2IE
INT1IE
—
INT2IF
INT1IF
bit 7
bit 0
bit 7
INT2IP: INT2 External Interrupt Priority bit
1
= High priority
0
= Low priority
bit 6
INT1IP: INT1 External Interrupt Priority bit
1
= High priority
0
= Low priority
bit 5
Unimplemented: Read as '0'
bit 4
INT2IE: INT2 External Interrupt Enable bit
1
= Enables the INT2 external interrupt
0
= Disables the INT2 external interrupt
bit 3
INT1IE: INT1 External Interrupt Enable bit
1
= Enables the INT1 external interrupt
0
= Disables the INT1 external interrupt
bit 2
Unimplemented: Read as '0'
bit 1
INT2IF: INT2 External Interrupt Flag bit
1
= The INT2 external interrupt occurred
(must be cleared in software)
0
= The INT2 external interrupt did not occur
bit 0
INT1IF: INT1 External Interrupt Flag bit
1
= The INT1 external interrupt occurred
(must be cleared in software)
0
= The INT1 external interrupt did not occur
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR reset
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
Note:
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit, or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows for software polling.