PIC18CXX2
DS39026C-page 62
2001 Microchip Technology Inc.
EXAMPLE 6-3:
16 x 16 UNSIGNED
MULTIPLY ROUTINE
used. The 32-bit result is stored in four registers,
RES3:RES0. To account for the sign bits of the argu-
ments, each argument pairs’ Most Significant bit (MSb)
is tested and the appropriate subtractions are done.
EQUATION 6-2:
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
RES3:RES0
=
ARG1H:ARG1L
ARG2H:ARG2L
=
(ARG1H
ARG2H 216)+
(ARG1H
ARG2L 28)+
(ARG1L
ARG2H 28)+
(ARG1L
ARG2L)+
(-1
ARG2H<7> ARG1H:ARG1L 216)+
(-1
ARG1H<7> ARG2H:ARG2L 216)
EXAMPLE 6-4:
16 x 16 SIGNED
MULTIPLY ROUTINE
MOVF
ARG1L, W
MULWF
ARG2L
; ARG1L * ARG2L ->
; PRODH:PRODL
MOVFF
PRODH, RES1 ;
MOVFF
PRODL, RES0 ;
;
MOVF
ARG1H, W
MULWF
ARG2H
; ARG1H * ARG2H ->
; PRODH:PRODL
MOVFF
PRODH, RES3 ;
MOVFF
PRODL, RES2 ;
;
MOVF
ARG1L, W
MULWF
ARG2H
; ARG1L * ARG2H ->
; PRODH:PRODL
MOVF
PRODL, W
;
ADDWF
RES1,
F
; Add cross
MOVF
PRODH, W
; products
ADDWFC
RES2,
F
;
CLRF
WREG,
F
;
ADDWFC
RES3,
F
;
MOVF
ARG1H, W
;
MULWF
ARG2L
; ARG1H * ARG2L ->
; PRODH:PRODL
MOVF
PRODL, W
;
ADDWF
RES1,
F
; Add cross
MOVF
PRODH, W
; products
ADDWFC
RES2,
F
;
CLRF
WREG,
F
;
ADDWFC
RES3,
F
;
MOVF
ARG1L, W
MULWF
ARG2L
; ARG1L * ARG2L ->
; PRODH:PRODL
MOVFF
PRODH, RES1 ;
MOVFF
PRODL, RES0 ;
;
MOVF
ARG1H, W
MULWF
ARG2H
; ARG1H * ARG2H ->
; PRODH:PRODL
MOVFF
PRODH, RES3 ;
MOVFF
PRODL, RES2 ;
;
MOVF
ARG1L, W
MULWF
ARG2H
; ARG1L * ARG2H ->
; PRODH:PRODL
MOVF
PRODL, W
;
ADDWF
RES1,
F
; Add cross
MOVF
PRODH, W
; products
ADDWFC
RES2,
F
;
CLRF
WREG,
F
;
ADDWFC
RES3,
F
;
MOVF
ARG1H, W
;
MULWF
ARG2L
; ARG1H * ARG2L ->
; PRODH:PRODL
MOVF
PRODL, W
;
ADDWF
RES1,
F
; Add cross
MOVF
PRODH, W
; products
ADDWFC
RES2, F
;
CLRF
WREG, F
;
ADDWFC
RES3, F
;
BTFSS
ARG2H, 7
; ARG2H:ARG2L neg?
BRA
SIGN_ARG1
; no, check ARG1
MOVF
ARG1L, W
;
SUBWF
RES2
;
MOVF
ARG1H, W
;
SUBWFB
RES3
;
SIGN_ARG1
BTFSS
ARG1H, 7
; ARG1H:ARG1L neg?
BRA
CONT_CODE
; no, done
MOVF
ARG2L, W
;
SUBWF
RES2
;
MOVF
ARG2H, W
;
SUBWFB
RES3
;
CONT_CODE
:
