參數(shù)資料
型號: PIC17C756A-16I/L
廠商: Microchip Technology
文件頁數(shù): 22/159頁
文件大?。?/td> 0K
描述: IC MCU OTP 16KX16 A/D PWM 68PLCC
產(chǎn)品培訓模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標準包裝: 19
系列: PIC® 17C
核心處理器: PIC
芯體尺寸: 8-位
速度: 16MHz
連通性: I²C,SPI,UART/USART
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 50
程序存儲器容量: 32KB(16K x 16)
程序存儲器類型: OTP
RAM 容量: 902 x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
數(shù)據(jù)轉換器: A/D 12x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 68-LCC(J 形引線)
包裝: 管件
配用: AC164308-ND - MODULE SKT FOR PM3 68PLCC
DVA17XL681-ND - DEVICE ADAPTER FOR PIC17C752
DM173001-ND - KIT DEVELOPMENT PICDEM17
AC174007-ND - MODULE SKT PROMATEII 68PLCC
AC164024-ND - ADAPTER PICSTART PLUS 68PLCC
Section 4 Clock Pulse Generator (CPG)
Page 86 of 1336
R01UH0025EJ0300 Rev. 3.00
Sep 24, 2010
SH7261 Group
PLL Frequency
Multiplier
Selectable Frequency Range (MHz)
Clock
Operating
Mode
FRQCR
Setting
PLL
Circuit 1
PLL
Circuit 2
Ratio of
Internal Clock
Frequencies
(I:B:P)
*
1
Input Clock
*
2
Output Clock
(CKIO Pin)
*
3
CPU Clock
(I
φ)
*
3
Bus Clock
(B
φ)
*
3
Peripheral
Clock (P
φ)
*
3
H'1404
ON (
×6)
OFF
6:1:1
20
120
20
H'1406
ON (
×6)
OFF
6:1:1/2
20
120
20
10
H'1414
ON (
×6)
OFF
3:1:1
20 to 33.33
60 to 100
20 to 33.33
H'1416
ON (
×6)
OFF
3:1:1/2
20 to 33.33
60 to 100
20 to 33.33
10 to 16.67
H'1424
ON (
×6)
OFF
2:1:1
20 to 33.33
40 to 66.67
20 to 33.33
H'1426
ON (
×6)
OFF
2:1:1/2
20 to 33.33
40 to 66.67
20 to 33.33
10 to 16.67
H'1444
ON (
×6)
OFF
1:1:1
20 to 33.33
20 to 33.33
H'1446
ON (
×6)
OFF
1:1:1/2
20 to 33.33
20 to 33.33
10 to 16.67
H'1515
ON (
×8)
OFF
4:1:1
20 to 25
80 to 100
20 to 25
H'1535
ON (
×8)
OFF
2:1:1
20 to 25
40 to 50
20 to 25
H'1555
ON (
×8)
OFF
1:1:1
20 to 25
20 to 25
Notes:
1. The ratio of clock frequencies, where the input clock frequency is assumed to be 1.
2. In modes 0 and 2, the frequency of the clock input from the EXTAL pin or the
frequency of the crystal resonator. In mode 3, the frequency of the clock input from
the CKIO pin.
3. Use an internal clock (I
φ) frequency of 120 MHz or lower for the regular
specifications and 100 MHz or lower for the wide-range specifications. Use a CKIO
pin or bus clock (B
φ) frequency of 60 MHz or lower. Pφ must be from 5 through 40
MHz.
Caution:
Do not use this LSI for frequency settings other than those in table 4.3.
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