參數(shù)資料
型號(hào)： PIC16LCR620AT-04I/SO
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 4 MHz, RISC MICROCONTROLLER, PDSO18
封裝： 0.300 INCH, PLASTIC, MS-013, SO-18
文件頁(yè)數(shù)： 82/128頁(yè)
文件大?。?/td> 3677K
代理商： PIC16LCR620AT-04I/SO
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2003 Microchip Technology Inc.
DS30235J-page 55
PIC16C62X
9.5
Interrupts
The PIC16C62X has 4 sources of interrupt:
External interrupt RB0/INT
TMR0 overflow interrupt
PORTB change interrupts (pins RB<7:4>)
Comparator interrupt
The interrupt control register (INTCON) records
individual interrupt requests in flag bits. It also has
individual and global interrupt enable bits.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. Individual interrupts can be
disabled through their corresponding enable bits in
INTCON register. GIE is cleared on RESET.
The “return from interrupt” instruction, RETFIE, exits
interrupt routine, as well as sets the GIE bit, which re-
enable RB0/INT interrupts.
The INT pin interrupt, the RB port change interrupt and
the TMR0 overflow interrupt flags are contained in the
INTCON register.
The peripheral interrupt flag is contained in the special
register PIR1. The corresponding interrupt enable bit is
contained in special registers PIE1.
When an interrupt is responded to, the GIE is cleared
to disable any further interrupt, the return address is
pushed into the stack and the PC is loaded with 0004h.
Once in the interrupt service routine, the source(s) of
the interrupt can be determined by polling the interrupt
flag bits. The interrupt flag bit(s) must be cleared in
software before re-enabling interrupts to avoid RB0/
INT recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs (Figure 9-16).
The latency is the same for one or two cycle
instructions. Once in the interrupt service routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid multiple interrupt requests.
FIGURE 9-15:
INTERRUPT LOGIC
Note 1: Individual interrupt flag bits are set
regardless
of
the
status
of
their
corresponding mask bit or the GIE bit.
2: When an instruction that clears the GIE
bit is executed, any interrupts that were
pending for execution in the next cycle
are ignored. The CPU will execute a NOP
in the cycle immediately following the
instruction which clears the GIE bit. The
interrupts which were ignored are still
pending to be serviced when the GIE bit
is set again.
RBIF
RBIE
T0IF
T0IE
INTF
INTE
GIE
PEIE
Wake-up
(If in SLEEP mode)
Interrupt
to CPU
CMIE
CMIF
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PIC16LF1454-E/ML 制造商:Microchip Technology Inc 功能描述:7 KB FLASH, 512 BYTES RAM, 48 MHZ INT. OSC, 12 I/0, ENHANCED - Rail/Tube 制造商:Microchip Technology Inc 功能描述:IC MCU 8BIT 7KB FLASH 16QFN 制造商:Microchip Technology Inc 功能描述:8-bit Microcontrollers - MCU 7KB Flsh 512b RAM 48MHz Int Osc 12 I/0
PIC16LF1454-E/P 制造商:Microchip Technology Inc 功能描述:7 KB FLASH, 512 BYTES RAM, 48 MHZ INT. OSC, 12 I/0, ENHANCED - Rail/Tube 制造商:Microchip Technology Inc 功能描述:IC MCU 8BIT 7KB FLASH 14PDIP
PIC16LF1454-E/SL 制造商:Microchip Technology Inc 功能描述:7 KB FLASH, 512 BYTES RAM, 48 MHZ INT. OSC, 12 I/0, ENHANCED - Rail/Tube 制造商:Microchip Technology Inc 功能描述:7 KB Flash, 512 bytes RAM, 48 MHz Int. Osc, 12 I/0, Enhanced Mid Range Core, USB 2.0, NanoWatt XLP
PIC16LF1454-E/ST 制造商:Microchip Technology Inc 功能描述:7 KB FLASH, 512 BYTES RAM, 48 MHZ INT. OSC, 12 I/0, ENHANCED - Rail/Tube 制造商:Microchip Technology Inc 功能描述:IC MCU 8BIT 7KB FLASH 14TSSOP
PIC16LF1454-I/ML 功能描述:8位微控制器 -MCU 7 KB Flash 512 bytes RAM 48 MHz Int Osc RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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