參數(shù)資料
型號: PIC16LC715T-04/SS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDSO20
封裝: 0.209 INCH, PLASTIC, SSOP-20
文件頁數(shù): 3/177頁
文件大?。?/td> 1650K
代理商: PIC16LC715T-04/SS
PIC16C71X
DS30272A-page 100
1997 Microchip Technology Inc.
Applicable Devices
710 71 711 715
FIGURE 11-7: A/D CONVERSION TIMING
TABLE 11-7:
A/D CONVERSION REQUIREMENTS
Param
No.
Sym Characteristic
Min
Typ
Max
Units
Conditions
130
TAD
A/D clock period
PIC16C710/711
1.6
s
TOSC based, VREF
≥ 3.0V
PIC16LC710/711
2.0
s
TOSC based, VREF full range
PIC16C710/711
2.0*
4.0
6.0
s
A/D RC mode
PIC16LC710/711
3.0*
6.0
9.0
s
A/D RC mode
131
TCNV Conversion time
(not including S/H time). (Note 1)
9.5
TAD
132
TACQ Acquisition time
Note 2
5*
20
s
The minimum time is the amplier
settling time. This may be used if the
"new" input voltage has not changed
by more than 1 LSb (i.e., 19.5 mV @
5.12V) from the last sampled voltage
(as stated on CHOLD).
134
TGO
Q4 to AD clock start
TOSC/2§
If the A/D clock source is selected as
RC, a time of TCY is added before the
A/D clock starts. This allows the
SLEEP
instruction to be executed.
135
TSWC Switching from convert
→ sample time
1.5§
TAD
*
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25
°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§
This specication ensured by design.
Note 1:
ADRES register may be read on the following TCY cycle.
2:
See Section 7.1 for min conditions.
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
(TOSC/2) (1)
7
6
5
4
3
2
1
0
Note 1:
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP
instruction to be executed.
1 Tcy
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