參數(shù)資料
型號: PIC16LC715T-04/SS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDSO20
封裝: 0.209 INCH, PLASTIC, SSOP-20
文件頁數(shù): 111/177頁
文件大?。?/td> 1650K
代理商: PIC16LC715T-04/SS
1997 Microchip Technology Inc.
DS30272A-page 39
PIC16C71X
The ADRES register contains the result of the A/D con-
version. When the A/D conversion is complete, the
result is loaded into the ADRES register, the GO/DONE
bit (ADCON0<2>) is cleared, and A/D interrupt ag bit
ADIF is set. The block diagram of the A/D module is
shown in Figure 7-4.
After the A/D module has been congured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 7.1.
After this acquisition time has elapsed the A/D conver-
sion can be started. The following steps should be fol-
lowed for doing an A/D conversion:
1.
Congure the A/D module:
Congure analog pins / voltage reference /
and digital I/O (ADCON1)
Select A/D input channel (ADCON0)
Select A/D conversion clock (ADCON0)
Turn on A/D module (ADCON0)
2.
Congure A/D interrupt (if desired):
Clear ADIF bit
Set ADIE bit
Set GIE bit
3.
Wait the required acquisition time.
4.
Start conversion:
Set GO/DONE bit (ADCON0)
5.
Wait for A/D conversion to complete, by either:
Polling for the GO/DONE bit to be cleared
OR
Waiting for the A/D interrupt
6.
Read A/D Result register (ADRES), clear bit
ADIF if required.
7.
For next conversion, go to step 1 or step 2 as
required. The A/D conversion time per bit is
dened as TAD. A minimum wait of 2TAD is
required before next acquisition starts.
FIGURE 7-4:
A/D BLOCK DIAGRAM
(Input voltage)
VIN
VREF
(Reference
voltage)
VDD
PCFG1:PCFG0
CHS1:CHS0
00
or
10
or
11
01
RA3/AN3/VREF
RA0/AN0
RA2/AN2
RA1/AN1
11
10
01
00
A/D
Converter
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