參數(shù)資料
型號: PIC16LC62BT-04I/ML
廠商: Microchip Technology
文件頁數(shù): 69/120頁
文件大?。?/td> 0K
描述: IC MCU OTP 2KX14 LV 28-QFN
標(biāo)準(zhǔn)包裝: 1,600
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 4MHz
連通性: I²C,SPI
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 22
程序存儲器容量: 3.5KB(2K x 14)
程序存儲器類型: OTP
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2.5 V ~ 5.5 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-VQFN 裸露焊盤
包裝: 帶卷 (TR)
其它名稱: PIC16LC62BT04I/ML
PIC16C62B/72A
DS35008B-page 52
Preliminary
1999 Microchip Technology Inc.
9.1
A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 9-2. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD). The
source impedance affects the offset voltage at the ana-
log input (due to pin leakage current). The maximum
recommended impedance for analog sources is 10
k
. After the analog input channel is selected
(changed), this acquisition must pass before the con-
version can be started.
To calculate the minimum acquisition time, TACQ, see
Equation 9-1. This equation calculates the acquisition
time to within 1/2 LSb error (512 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified accuracy.
In general;
Assuming RS
= 10k
Vdd
= 3.0V (RSS = 10k
)
Temp. = 50
°C (122°F)
TACQ
≈ 13.0 Sec
By increasing VDD and reducing RS and Temp., TACQ
can be substantially reduced.
FIGURE 9-2:
ANALOG INPUT MODEL
EQUATION 9-1:
ACQUISITION TIME
Note:
When the conversion is started, the hold-
ing capacitor is disconnected from the
input pin.
TACQ
=
Amplifier Settling Time +
Hold Capacitor Charging Time +
Temperature Coefficient
TAMP + TC + TCOFF
TAMP = 5
S
TC = - (51.2pF)(1k
+ RSS + RS) In(1/511)
TCOFF = (Temp -25
°C)(0.05S/°C)
CPIN
VA
Rs
ANx
5 pF
VDD
VT = 0.6V
I leakage
RIC
≤ 1k
Sampling
Switch
SS
RSS
CHOLD
= DAC capacitance
VSS
6V
RSS
5V
4V
3V
2V
5 678 9 10 11
(k
)
VDD
= 51.2 pF
± 500 nA
Legend CPIN
VT
I leakage
RIC
SS
CHOLD
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
various junctions
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