2007 Microchip Technology Inc.
DS41250F-page 85
PIC16F913/914/916/917/946
3.9.1
PIN DESCRIPTIONS AND
DIAGRAMS
Each PORTG pin is multiplexed with other functions. The
pins and their combined functions are briefly described
here. For specific information about individual functions,
refer to the appropriate section in this data sheet.
3.9.1.1
RG0/SEG36
pin is configurable to function as one of the following:
a general purpose I/O
an analog output for the LCD
3.9.1.2
RG1/SEG37
pin is configurable to function as one of the following:
a general purpose I/O
an analog output for the LCD
3.9.1.3
RG2/SEG38
pin is configurable to function as one of the following:
a general purpose I/O
an analog output for the LCD
3.9.1.4
RG3/SEG39
pin is configurable to function as one of the following:
a general purpose I/O
an analog output for the LCD
3.9.1.5
RG4/SEG40
pin is configurable to function as one of the following:
a general purpose I/O
an analog output for the LCD
3.9.1.6
RG5/SEG41
pin is configurable to function as one of the following:
a general purpose I/O
an analog output for the LCD
FIGURE 3-30:
BLOCK DIAGRAM OF RG<5:0>
Data Bus
WR PORTG
WR TRISG
RD PORTG
SEG<41:36>
Schmitt
Trigger
I/O Pin
Data Latch
TRIS Latch
Q
D
Q
CK
Q
D
Q
CK
RD TRISG
SE<41:36> and LCDEN
VDD
VSS