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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� PIC16F870-I/SS
寤犲晢锛� Microchip Technology
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2003 Microchip Technology Inc.
DS30569B-page 15
PIC16F870/871
Bank 2
100h(4)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
101h
TMR0
Timer0 Module鈥檚 Register
xxxx xxxx
uuuu uuuu
102h(4)
PCL
Program Counter's (PC) Least Significant Byte
0000 0000
103h(4)
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx
000q quuu
104h(4)
FSR
Indirect Data Memory Address Pointer
xxxx xxxx
uuuu uuuu
105h
鈥�
Unimplemented
鈥�
106h
PORTB
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx
uuuu uuuu
107h
鈥�
Unimplemented
鈥�
108h
鈥�
Unimplemented
鈥�
109h
鈥�
Unimplemented
鈥�
10Ah(1,4)
PCLATH
鈥�
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
10Bh(4)
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
10Ch
EEDATA
EEPROM Data Register
xxxx xxxx
uuuu uuuu
10Dh
EEADR
EEPROM Address Register
xxxx xxxx
uuuu uuuu
10Eh
EEDATH
鈥�
EEPROM Data Register High Byte
xxxx xxxx
uuuu uuuu
10Fh
EEADRH
鈥�
EEPROM Address Register High Byte
xxxx xxxx
uuuu uuuu
Bank 3
180h(4)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
181h
OPTION_REG
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
182h(4)
PCL
Program Counter's (PC) Least Significant Byte
0000 0000
183h(4)
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx
000q quuu
184h(4)
FSR
Indirect Data Memory Address Pointer
xxxx xxxx
uuuu uuuu
185h
鈥�
Unimplemented
鈥�
186h
TRISB
PORTB Data Direction Register
1111 1111
187h
鈥�
Unimplemented
鈥�
188h
鈥�
Unimplemented
鈥�
189h
鈥�
Unimplemented
鈥�
18Ah(1,4)
PCLATH
鈥�
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
18Bh(4)
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
18Ch
EECON1
EEPGD
鈥�
WRERR
WREN
WR
RD
x--- x000
x--- u000
18Dh
EECON2
EEPROM Control Register2 (not a physical register)
---- ----
18Eh
鈥�
Reserved maintain clear
0000 0000
18Fh
鈥�
Reserved maintain clear
0000 0000
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
RESETS(2)
Legend:
x
= unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as 鈥�0鈥�.
Note
1:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
2:
Other (non Power-up) Resets include external RESET through MCLR and Watchdog Timer Reset.
3:
Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4:
These registers can be addressed from any bank.
5:
PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices, read as 鈥�0鈥�.
鐩搁棞PDF璩囨枡
PDF鎻忚堪
XF2C-3955-41A CONNECTOR FPC 39POS 0.3MM SMD
XF2C-3555-41A CONNECTOR FPC 35POS 0.3MM SMD
XF2C-2955-41A CONNECTOR FPC 29POS 0.3MM SMD
XF2C-2555-41A CONNECTOR FPC 25POS 0.3MM SMD
XF2C-2155-41A CONNECTOR FPC 21POS 0.3MM SMD
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