參數(shù)資料
型號: PIC16F628-04I/SS
廠商: Microchip Technology
文件頁數(shù): 89/170頁
文件大?。?/td> 0K
描述: IC MCU FLASH 2KX14 COMP 20SSOP
產(chǎn)品培訓模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標準包裝: 67
系列: PIC® 16F
核心處理器: PIC
芯體尺寸: 8-位
速度: 4MHz
連通性: UART/USART
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 16
程序存儲器容量: 3.5KB(2K x 14)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 128 x 8
RAM 容量: 224 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-SSOP(0.209",5.30mm 寬)
包裝: 管件
配用: XLT20SS-1-ND - SOCKET TRANSITION 18DIP 20SSOP
AC164307-ND - MODULE SKT FOR PM3 28SSOP
2003 Microchip Technology Inc.
Preliminary
DS40300C-page 23
PIC16F62X
3.2.2.5
PIR1 Register
This register contains interrupt flag bits.
REGISTER 3-5:
PIR1 REGISTER (ADDRESS: 0Ch)
Note:
Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable
bit,
GIE
(INTCON<7>).
User
software should ensure the appropriate
interrupt flag bits are clear prior to enabling
an interrupt.
R/W-0
R-0
U-0
R/W-0
EEIF
CMIF
RCIF
TXIF
CCP1IF
TMR2IF
TMR1IF
bit 7
bit 0
bit 7
EEIF: EEPROM Write Operation Interrupt Flag bit
1
= The write operation completed (must be cleared in software)
0
= The write operation has not completed or has not been started
bit 6
CMIF: Comparator Interrupt Flag bit
1
= Comparator output has changed
0
= Comparator output has not changed
bit 5
RCIF: USART Receive Interrupt Flag bit
1
= The USART receive buffer is full
0
= The USART receive buffer is empty
bit 4
TXIF: USART Transmit Interrupt Flag bit
1
= The USART transmit buffer is empty
0
= The USART transmit buffer is full
bit 3
Unimplemented: Read as ‘0’
bit 2
CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1
= A TMR1 register capture occurred (must be cleared in software)
0
= No TMR1 register capture occurred
Compare Mode
1
= A TMR1 register compare match occurred (must be cleared in software)
0
= No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1
= TMR2 to PR2 match occurred (must be cleared in software)
0
= No TMR2 to PR2 match occurred
bit 0
TMR1IF: TMR1 Overflow Interrupt Flag bit
1
= TMR1 register overflowed (must be cleared in software)
0
= TMR1 register did not overflow
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
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