
PIC16(L)F1512/3
DS41624B-page 248
Preliminary
2012 Microchip Technology Inc.
FIGURE 22-2:
EUSART RECEIVE BLOCK DIAGRAM
The operation of the EUSART module is controlled
through three registers:
Transmit Status and Control (TXSTA)
Receive Status and Control (RCSTA)
Baud Rate Control (BAUDCON)
These
registers
are
detailed
in
When the receiver or transmitter section is not enabled
then the corresponding RX or TX pin may be used for
general purpose input and output.
RX/DT pin
Pin Buffer
and Control
SPEN
Data
Recovery
CREN
OERR
FERR
RSR Register
MSb
LSb
RX9D
RCREG Register
FIFO
Interrupt
RCIF
RCIE
Data Bus
8
Stop
Start
(8)
7
1
0
RX9
SPBRGL
SPBRGH
BRG16
RCIDL
FOSC
÷ n
n
+ 1
Multiplier
x4
x16 x64
SYNC
1X00 0
BRGH
X110 0
BRG16
X101 0
Baud Rate Generator