100h(4) INDF Addressing this location" />
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  • 參數(shù)資料
    型號: PIC16CR77T-I/PT
    廠商: Microchip Technology
    文件頁數(shù): 86/172頁
    文件大?。?/td> 0K
    描述: IC PIC MCU 8KX14 44TQFP
    標(biāo)準(zhǔn)包裝: 1,200
    系列: PIC® 16C
    核心處理器: PIC
    芯體尺寸: 8-位
    速度: 20MHz
    連通性: I²C,SPI,UART/USART
    外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
    輸入/輸出數(shù): 33
    程序存儲器容量: 14KB(8K x 14)
    程序存儲器類型: ROM
    RAM 容量: 368 x 8
    電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
    數(shù)據(jù)轉(zhuǎn)換器: A/D 8x8b
    振蕩器型: 內(nèi)部
    工作溫度: -40°C ~ 85°C
    封裝/外殼: 44-TQFP
    包裝: 帶卷 (TR)
    PIC16CR7X
    DS21993C-page 18
    2007 Microchip Technology Inc.
    Bank 2
    100h(4)
    INDF
    Addressing this location uses contents of FSR to address data memory (not a physical register)
    0000 0000
    101h
    TMR0
    Timer0 Module Register
    xxxx xxxx
    102h(4)
    PCL
    Program Counter (PC) Least Significant Byte
    0000 0000
    103h(4)
    STATUS
    IRP
    RP1
    RP0
    TO
    PD
    ZDC
    C
    0001 1xxx
    104h(4)
    FSR
    Indirect Data Memory Address Pointer
    xxxx xxxx
    105h
    Unimplemented
    106h
    PORTB
    PORTB Data Latch when written: PORTB pins when read
    xxxx xxxx
    107h
    Unimplemented
    108h
    Unimplemented
    109h
    Unimplemented
    10Ah(1,4) PCLATH
    Write Buffer for the upper 5 bits of the Program Counter
    ---0 0000
    10Bh(4)
    INTCON
    GIE
    PEIE
    TMR0IE
    INTE
    RBIE
    TMR0IF
    INTF
    RBIF
    0000 000x
    10Ch
    PMDATA
    Data Register Low Byte
    xxxx xxxx
    10Dh
    PMADR
    Address Register Low Byte
    xxxx xxxx
    10Eh
    PMDATH
    Data Register High Byte
    xxxx xxxx
    10Fh
    PMADRH
    Address Register High Byte
    xxxx xxxx
    Bank 3
    180h(4)
    INDF
    Addressing this location uses contents of FSR to address data memory (not a physical register)
    0000 0000
    181h
    OPTION_REG
    RBPU
    INTEDG
    T0CS
    T0SE
    PSA
    PS2
    PS1
    PS0
    1111 1111
    182h(4)
    PCL
    Program Counter (PC) Least Significant Byte
    0000 0000
    183h(4)
    STATUS
    IRP
    RP1
    RP0
    TO
    PD
    ZDC
    C
    0001 1xxx
    184h(4)
    FSR
    Indirect Data Memory Address Pointer
    xxxx xxxx
    185h
    Unimplemented
    186h
    TRISB
    PORTB Data Direction Register
    1111 1111
    187h
    Unimplemented
    188h
    Unimplemented
    189h
    Unimplemented
    18Ah(1,4) PCLATH
    Write Buffer for the upper 5 bits of the Program Counter
    ---0 0000
    18Bh(4)
    INTCON
    GIE
    PEIE
    TMR0IE
    INTE
    RBIE
    TMR0IF
    INTF
    RBIF
    0000 000x
    18Ch
    PMCON1
    (6)
    —RD
    1--- ---0
    18Dh
    Unimplemented
    18Eh
    Reserved maintain clear
    0000 0000
    18Fh
    Reserved maintain clear
    0000 0000
    TABLE 2-1:
    SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
    Address
    Name
    Bit 7
    Bit 6
    Bit 5
    Bit 4
    Bit 3
    Bit 2
    Bit 1
    Bit 0
    Value on
    POR,
    BOR
    Details
    on page
    Legend:
    x
    = unknown, u = unchanged, q = value depends on condition, – = unimplemented, read as ‘0’, r = reserved.
    Shaded locations are unimplemented, read as ‘0’.
    Note
    1:
    The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
    contents are transferred to the upper byte of the program counter during branches (CALL or GOTO).
    2:
    Other (non Power-up) Resets include external Reset through MCLR and Watchdog Timer Reset.
    3:
    Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
    4:
    These registers can be addressed from any bank.
    5:
    PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
    6:
    This bit always reads as a ‘1’.
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