參數(shù)資料
型號(hào): PIC16CE625T-30/SS
廠商: Microchip Technology
文件頁(yè)數(shù): 54/100頁(yè)
文件大小: 0K
描述: IC MCU OTP 2KX14 EE COMP 20SSOP
標(biāo)準(zhǔn)包裝: 1,600
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 30MHz
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,WDT
輸入/輸出數(shù): 13
程序存儲(chǔ)器容量: 3.5KB(2K x 14)
程序存儲(chǔ)器類型: OTP
EEPROM 大?。?/td> 128 x 8
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 20-SSOP(0.209",5.30mm 寬)
包裝: 帶卷 (TR)
其它名稱: PIC16CE625T30/SS
1999 Microchip Technology Inc.
DS40182C-page 47
PIC16CE62X
9.0
VOLTAGE REFERENCE
MODULE
The Voltage Reference is a 16-tap resistor ladder
network that provides a selectable voltage reference.
The resistor ladder is segmented to provide two ranges
of VREF values and has a power-down function to
conserve power when the reference is not being used.
The VRCON register controls the operation of the
reference as shown in Register 9-1. The block diagram
is given in Figure 9-1.
9.1
Configuring the Voltage Reference
The Voltage Reference can output 16 distinct voltage
levels for each range.
The equations used to calculate the output of the
Voltage Reference are as follows:
if VRR = 1: VREF = (VR<3:0>/24) x VDD
if VRR = 0: VREF = (VDD x 1/4) + (VR<3:0>/32) x VDD
The setting time of the Voltage Reference must be
considered
when
changing
the
VREF
output
(Table 13-1). Example 9-1 shows an example of how to
configure the Voltage Reference for an output voltage
of 1.25V with VDD = 5.0V.
REGISTER 9-1:
VRCON REGISTER (ADDRESS 9Fh)
FIGURE 9-1:
VOLTAGE REFERENCE BLOCK DIAGRAM
R/W-0
U-0
R/W-0
VREN
VROE
VRR
—VR3
VR2
VR1
VR0
R
= Readable bit
W = Writable bit
U
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7
bit0
bit 7:
VREN: VREF Enable
1
= VREF circuit powered on
0
= VREF circuit powered down, no IDD drain
bit 6:
VROE: VREF Output Enable
1
= VREF is output on RA2 pin
0
= VREF is disconnected from RA2 pin
bit 5:
VRR: VREF Range selection
1
= Low Range
0
= High Range
bit 4:
Unimplemented: Read as ’0’
bit 3-0: VR<3:0>: VREF value selection 0
≤ VR [3:0] ≤ 15
when VRR = 1: VREF = (VR<3:0>/ 24) * VDD
when VRR = 0: VREF = 1/4 * VDD + (VR<3:0>/ 32) * VDD
Note:
R is defined in Table 13-2.
VRR
8R
VR3
VR0
(From VRCON<3:0>)
16-1 Analog Mux
8R
R
VREN
VREF
16 Stages
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