- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗3859 > PIC16C711-04/SS (Microchip Technology)IC MCU OTP 1KX14 A/D 20SSOP PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | PIC16C711-04/SS |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 74/177闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MCU OTP 1KX14 A/D 20SSOP |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Asynchronous Stimulus |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 67 |
| 绯诲垪锛� | PIC® 16C |
| 鏍稿績铏曠悊鍣細 | PIC |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 4MHz |
| 澶栧湇瑷�(sh猫)鍌欙細 | 娆犲妾㈡脯(c猫)/寰�(f霉)浣嶏紝POR锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 13 |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 | 1.75KB锛�1K x 14锛� |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 | OTP |
| RAM 瀹归噺锛� | 68 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 4 V ~ 6 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 4x8b |
| 鎸暕鍣ㄥ瀷锛� | 澶栭儴 |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 灏佽/澶栨锛� | 20-SSOP锛�0.209"锛�5.30mm 瀵級 |
| 鍖呰锛� | 绠′欢 |
| 閰嶇敤锛� | XLT20SS-1-ND - SOCKET TRANSITION 18DIP 20SSOP AC164307-ND - MODULE SKT FOR PM3 28SSOP ISPICR1-ND - ADAPTER IN-CIRCUIT PROGRAMMING 309-1016-ND - ADAPTER 20-SSOP TO 18-DIP |
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165
7593L鈥揂VR鈥�09/12
AT90USB64/128
The clock source for Timer/Counter2 is named clk
T2S. clkT2S is by default connected to the main
system I/O clock clk
IO. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously
clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter
(RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from Port C. A crystal can
then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock
source for Timer/Counter2. The Oscillator is optimized for use with a 32.768kHz crystal. Apply-
ing an external clock source to TOSC1 is not recommended.
For Timer/Counter2, the possible prescaled selections are: clk
T2S/8, clkT2S/32, clkT2S/64,
clk
T2S/128, clkT2S/256, and clkT2S/1024. Additionally, clkT2S as well as 0 (stop) may be selected.
Setting the PSRASY bit in GTCCR resets the prescaler. This allows the user to operate with a
predictable prescaler.
16.10.1
GTCCR 鈥� General Timer/Counter Control Register
Bit 1 鈥� PSRASY: Prescaler Reset Timer/Counter2
When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally cleared
immediately by hardware. If the bit is written when Timer/Counter2 is operating in asynchronous
mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by
hardware if the TSM bit is set. Refer to the description of the Section 鈥淕TCCR 鈥� General
Timer/Counter Control Register鈥� on page 97 for a description of the Timer/Counter Synchroniza-
tion mode.
Bit
7
6
5
4
3
2
1
0
TSM
鈥�
鈥揚SRA-
SY
PSRSY
NC
GTCCR
Read/write
R/W
R
R/W
Initial value
0
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