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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | PIC16C711-04/SS |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋佹暩(sh霉)锛� | 68/177闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MCU OTP 1KX14 A/D 20SSOP |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Asynchronous Stimulus |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 67 |
| 绯诲垪锛� | PIC® 16C |
| 鏍稿績铏曠悊鍣細 | PIC |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 4MHz |
| 澶栧湇瑷�(sh猫)鍌欙細 | 娆犲妾㈡脯/寰�(f霉)浣�锛孭OR锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 13 |
| 绋嬪簭瀛樺劜鍣ㄥ閲忥細 | 1.75KB锛�1K x 14锛� |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | OTP |
| RAM 瀹归噺锛� | 68 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 4 V ~ 6 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 4x8b |
| 鎸暕鍣ㄥ瀷锛� | 澶栭儴 |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 灏佽/澶栨锛� | 20-SSOP锛�0.209"锛�5.30mm 瀵級 |
| 鍖呰锛� | 绠′欢 |
| 閰嶇敤锛� | XLT20SS-1-ND - SOCKET TRANSITION 18DIP 20SSOP AC164307-ND - MODULE SKT FOR PM3 28SSOP ISPICR1-ND - ADAPTER IN-CIRCUIT PROGRAMMING 309-1016-ND - ADAPTER 20-SSOP TO 18-DIP |
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PIC16C71X
DS30272A-page 16
1997 Microchip Technology Inc.
Bank 1
80h(1)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
81h
OPTION
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
82h(1)
PCL
Program Counter's (PC) Least Signicant Byte
0000 0000
83h(1)
STATUS
IRP(4)
RP1(4)
RP0
TO
PD
Z
DC
C
0001 1xxx
000q quuu
84h(1)
FSR
Indirect data memory address pointer
xxxx xxxx
uuuu uuuu
85h
TRISA
鈥�
PORTA Data Direction Register
--11 1111
86h
TRISB
PORTB Data Direction Register
1111 1111
87h
鈥�
Unimplemented
鈥�
88h
鈥�
Unimplemented
鈥�
89h
鈥�
Unimplemented
鈥�
8Ah(1,2)
PCLATH
鈥�
Write Buffer for the upper 5 bits of the PC
---0 0000
8Bh(1)
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
8Ch
PIE1
鈥�
ADIE
鈥�
-0-- ----
8Dh
鈥�
Unimplemented
鈥�
8Eh
PCON
MPEEN
鈥�
PER
POR
BOR
u--- -1qq
u--- -1uu
8Fh
鈥�
Unimplemented
鈥�
90h
鈥�
Unimplemented
鈥�
91h
鈥�
Unimplemented
鈥�
92h
鈥�
Unimplemented
鈥�
93h
鈥�
Unimplemented
鈥�
94h
鈥�
Unimplemented
鈥�
95h
鈥�
Unimplemented
鈥�
96h
鈥�
Unimplemented
鈥�
97h
鈥�
Unimplemented
鈥�
98h
鈥�
Unimplemented
鈥�
99h
鈥�
Unimplemented
鈥�
9Ah
鈥�
Unimplemented
鈥�
9Bh
鈥�
Unimplemented
鈥�
9Ch
鈥�
Unimplemented
鈥�
9Dh
鈥�
Unimplemented
鈥�
9Eh
鈥�
Unimplemented
鈥�
9Fh
ADCON1
鈥�
PCFG1
PCFG0
---- --00
TABLE 4-2:
PIC16C715 SPECIAL FUNCTION REGISTER SUMMARY (Cont.鈥檇)
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR, PER
Value on all
other resets
(3)
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as 鈥�0鈥�.
Note 1:
These registers can be addressed from either bank.
2:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
3:
Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
4:
The IRP and RP1 bits are reserved on the PIC16C715, always maintain these bits clear.
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