T2S. clk
參數(shù)資料
型號: PIC16C710-04/SO
廠商: Microchip Technology
文件頁數(shù): 74/177頁
文件大小: 0K
描述: IC MCU OTP 512X14 A/D 18SOIC
產(chǎn)品培訓模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標準包裝: 42
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 4MHz
外圍設(shè)備: 欠壓檢測/復位,POR,WDT
輸入/輸出數(shù): 13
程序存儲器容量: 896B(512 x 14)
程序存儲器類型: OTP
RAM 容量: 36 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x8b
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 18-SOIC(0.295",7.50mm 寬)
包裝: 管件
配用: XLT18SO-1-ND - SOCKET TRANSITION 18SOIC 300MIL
ISPICR1-ND - ADAPTER IN-CIRCUIT PROGRAMMING
309-1011-ND - ADAPTER 18-SOIC TO 18-DIP
309-1010-ND - ADAPTER 18-SOIC TO 18-DIP
AC164010-ND - MODULE SKT PROMATEII DIP/SOIC
其它名稱: PIC16C710-04/SOR
PIC16C710-04/SOR-ND
165
7593L–AVR–09/12
AT90USB64/128
The clock source for Timer/Counter2 is named clk
T2S. clkT2S is by default connected to the main
system I/O clock clk
IO. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously
clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter
(RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from Port C. A crystal can
then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock
source for Timer/Counter2. The Oscillator is optimized for use with a 32.768kHz crystal. Apply-
ing an external clock source to TOSC1 is not recommended.
For Timer/Counter2, the possible prescaled selections are: clk
T2S/8, clkT2S/32, clkT2S/64,
clk
T2S/128, clkT2S/256, and clkT2S/1024. Additionally, clkT2S as well as 0 (stop) may be selected.
Setting the PSRASY bit in GTCCR resets the prescaler. This allows the user to operate with a
predictable prescaler.
16.10.1
GTCCR – General Timer/Counter Control Register
Bit 1 – PSRASY: Prescaler Reset Timer/Counter2
When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally cleared
immediately by hardware. If the bit is written when Timer/Counter2 is operating in asynchronous
mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by
hardware if the TSM bit is set. Refer to the description of the Section “GTCCR – General
Timer/Counter Control Register” on page 97 for a description of the Timer/Counter Synchroniza-
tion mode.
Bit
7
6
5
4
3
2
1
0
TSM
–PSRA-
SY
PSRSY
NC
GTCCR
Read/write
R/W
R
R/W
Initial value
0
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