參數(shù)資料
型號(hào): PIC16C710-04/SO
廠商: Microchip Technology
文件頁數(shù): 121/177頁
文件大?。?/td> 0K
描述: IC MCU OTP 512X14 A/D 18SOIC
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 42
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 4MHz
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,WDT
輸入/輸出數(shù): 13
程序存儲(chǔ)器容量: 896B(512 x 14)
程序存儲(chǔ)器類型: OTP
RAM 容量: 36 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x8b
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 18-SOIC(0.295",7.50mm 寬)
包裝: 管件
配用: XLT18SO-1-ND - SOCKET TRANSITION 18SOIC 300MIL
ISPICR1-ND - ADAPTER IN-CIRCUIT PROGRAMMING
309-1011-ND - ADAPTER 18-SOIC TO 18-DIP
309-1010-ND - ADAPTER 18-SOIC TO 18-DIP
AC164010-ND - MODULE SKT PROMATEII DIP/SOIC
其它名稱: PIC16C710-04/SOR
PIC16C710-04/SOR-ND
PIC16C71X
DS30272A-page 48
1997 Microchip Technology Inc.
FIGURE 8-2:
CONFIGURATION WORD, PIC16C710/711
FIGURE 8-3:
CONFIGURATION WORD, PIC16C715
CP0
BODEN
CP0
PWRTE WDTE FOSC1 FOSC0
Register:
CONFIG
Address
2007h
bit13
bit0
bit 13-7 CP0: Code protection bits (2)
5-4: 1 = Code protection off
0 = All memory is code protected, but 00h - 3Fh is writable
bit 6:
BODEN: Brown-out Reset Enable bit (1)
1 = BOR enabled
0 = BOR disabled
bit 3:
PWRTE: Power-up Timer Enable bit (1)
1 = PWRT disabled
0 = PWRT enabled
bit 2:
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0:
FOSC1:FOSC0: Oscillator Selection bits
11
= RC oscillator
10
= HS oscillator
01
= XT oscillator
00
= LP oscillator
Note 1:
Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE.
Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled.
2:
All of the CP0 bits have to be given the same value to enable the code protection scheme listed.
CP1
CP0
CP1
CP0
CP1
CP0 MPEEN BODEN
CP1
CP0
PWRTE WDTE FOSC1 FOSC0
Register:
CONFIG
Address
2007h
bit13
bit0
bit 13-8
CP1:CP0: Code Protection bits (2)
5-4:
11
= Code protection off
10
= Upper half of program memory code protected
01
= Upper 3/4th of program memory code protected
00
= All memory is code protected
bit 7:
MPEEN: Memory Parity Error Enable
1 = Memory Parity Checking is enabled
0 = Memory Parity Checking is disabled
bit 6:
BODEN: Brown-out Reset Enable bit (1)
1 = BOR enabled
0 = BOR disabled
bit 3:
PWRTE: Power-up Timer Enable bit (1)
1 = PWRT disabled
0 = PWRT enabled
bit 2:
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0:
FOSC1:FOSC0: Oscillator Selection bits
11
= RC oscillator
10
= HS oscillator
01
= XT oscillator
00
= LP oscillator
Note 1:
Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE.
Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled.
2:
All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
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