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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | PIC16C710-04/P |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋佹暩(sh霉)锛� | 42/177闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC MCU OTP 512X14 A/D 18DIP |
| 鐢㈠搧鍩硅〒妯″锛� | Asynchronous Stimulus 8-bit PIC® Microcontroller Portfolio |
| 妯欐簴鍖呰锛� | 25 |
| 绯诲垪锛� | PIC® 16C |
| 鏍稿績铏曠悊鍣細 | PIC |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 4MHz |
| 澶栧湇瑷倷锛� | 娆犲妾㈡脯/寰╀綅锛孭OR锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 13 |
| 绋嬪簭瀛樺劜鍣ㄥ閲忥細 | 896B锛�512 x 14锛� |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | OTP |
| RAM 瀹归噺锛� | 36 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 4 V ~ 6 V |
| 鏁�(sh霉)鎿�(j霉)杞夋彌鍣細 | A/D 4x8b |
| 鎸暕鍣ㄥ瀷锛� | 澶栭儴 |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 灏佽/澶栨锛� | 18-DIP锛�0.300"锛�7.62mm锛� |
| 鍖呰锛� | 绠′欢 |
| 閰嶇敤锛� | ISPICR1-ND - ADAPTER IN-CIRCUIT PROGRAMMING 309-1059-ND - ADAPTER 18 ZIF BD W/18SO PLUGS DVA16XP180-ND - ADAPTER DEVICE FOR MPLAB-ICE AC164010-ND - MODULE SKT PROMATEII DIP/SOIC |
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7593L鈥揂VR鈥�09/12
AT90USB64/128
Figure 15-13. Timer/Counter timing diagram, with prescaler (f
clk_I/O/8).
15.10 16-bit Timer/Counter register description
15.10.1
TCCR1A 鈥� Timer/Counter1 Control Register A
15.10.2
TCCR3A 鈥� Timer/Counter3 Control Register A
Bit 7:6 鈥� COMnA1:0: Compare Output Mode for Channel A
Bit 5:4 鈥� COMnB1:0: Compare Output Mode for Channel B
Bit 3:2 鈥� COMnC1:0: Compare Output Mode for Channel C
The COMnA1:0, COMnB1:0, and COMnC1:0 control the output compare pins (OCnA, OCnB,
and OCnC respectively) behavior. If one or both of the COMnA1:0 bits are written to one, the
OCnA output overrides the normal port functionality of the I/O pin it is connected to. If one or
both of the COMnB1:0 bits are written to one, the OCnB output overrides the normal port func-
tionality of the I/O pin it is connected to. If one or both of the COMnC1:0 bits are written to one,
the OCnC output overrides the normal port functionality of the I/O pin it is connected to. How-
ever, note that the Data Direction Register (DDR) bit corresponding to the OCnA, OCnB or
OCnC pin must be set in order to enable the output driver.
TOVn(FPWM)
and ICF n(if used
as TOP)
OCRnx
(update at TOP)
TCNTn
(CTC and FPWM)
TCNTn
(PC and PFC PWM)
TOP - 1
TOP
TOP - 1
TOP - 2
Old OCRnx value
New OCRnx value
TOP - 1
TOP
BOTTOM
BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O /8)
Bit
7
65
43
2
1
0
COM1A1
COM1A0
COM1B1
COM1B0
COM1C1
COM1C0
WGM11
WGM10
TCCR1A
Read/write
R/W
Initial value
00
000
0
Bit
7
65
43
2
1
0
COM3A1
COM3A0
COM3B1
COM3B0
COM3C1
COM3C0
WGM31
WGM30
TCCR3A
Read/write
R/W
Initial value
00
000
0
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鐩搁棞浠ｇ悊鍟�/鎶€琛撳弮鏁�(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
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| PIC16C710-20/P | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU .875KB 36 RAM 13 I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT |
| PIC16C710-20/P | 鍒堕€犲晢:Microchip Technology Inc 鍔熻兘鎻忚堪:IC 8BIT CMOS MCU 16C710 DIP18 |
| PIC16C710-20/SO | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU .875KB 36 RAM 13 I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT |
| PIC16C710-20/SS | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU .875KB 36 RAM 13 I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT |
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