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    參數資料
    型號: PIC16C710-04/P
    廠商: Microchip Technology
    文件頁數: 2/177頁
    文件大小: 0K
    描述: IC MCU OTP 512X14 A/D 18DIP
    產品培訓模塊: Asynchronous Stimulus
    8-bit PIC® Microcontroller Portfolio
    標準包裝: 25
    系列: PIC® 16C
    核心處理器: PIC
    芯體尺寸: 8-位
    速度: 4MHz
    外圍設備: 欠壓檢測/復位,POR,WDT
    輸入/輸出數: 13
    程序存儲器容量: 896B(512 x 14)
    程序存儲器類型: OTP
    RAM 容量: 36 x 8
    電壓 - 電源 (Vcc/Vdd): 4 V ~ 6 V
    數據轉換器: A/D 4x8b
    振蕩器型: 外部
    工作溫度: 0°C ~ 70°C
    封裝/外殼: 18-DIP(0.300",7.62mm)
    包裝: 管件
    配用: ISPICR1-ND - ADAPTER IN-CIRCUIT PROGRAMMING
    309-1059-ND - ADAPTER 18 ZIF BD W/18SO PLUGS
    DVA16XP180-ND - ADAPTER DEVICE FOR MPLAB-ICE
    AC164010-ND - MODULE SKT PROMATEII DIP/SOIC
    PIC16C71X
    DS30272A-page 10
    1997 Microchip Technology Inc.
    3.1
    Clocking Scheme/Instruction Cycle
    The clock input (from OSC1) is internally divided by
    four to generate four non-overlapping quadrature
    clocks namely Q1, Q2, Q3 and Q4. Internally, the pro-
    gram counter (PC) is incremented every Q1, the
    instruction is fetched from the program memory and
    latched into the instruction register in Q4. The instruc-
    tion is decoded and executed during the following Q1
    through Q4. The clocks and instruction execution ow
    is shown in Figure 3-2.
    3.2
    Instruction Flow/Pipelining
    An “Instruction Cycle” consists of four Q cycles (Q1,
    Q2, Q3 and Q4). The instruction fetch and execute are
    pipelined such that fetch takes one instruction cycle
    while decode and execute takes another instruction
    cycle. However, due to the pipelining, each instruction
    effectively executes in one cycle. If an instruction
    causes the program counter to change (e.g. GOTO) then
    two cycles are required to complete the instruction
    A fetch cycle begins with the program counter (PC)
    incrementing in Q1.
    In the execution cycle, the fetched instruction is latched
    into the “Instruction Register” (IR) in cycle Q1. This
    instruction is then decoded and executed during the
    Q2, Q3, and Q4 cycles. Data memory is read during Q2
    (operand read) and written during Q4 (destination
    write).
    FIGURE 3-2:
    CLOCK/INSTRUCTION CYCLE
    EXAMPLE 3-1:
    INSTRUCTION PIPELINE FLOW
    Q1
    Q2
    Q3
    Q4
    Q1
    Q2
    Q3
    Q4
    Q1
    Q2
    Q3
    Q4
    OSC1
    Q1
    Q2
    Q3
    Q4
    PC
    OSC2/CLKOUT
    (RC mode)
    PC
    PC+1
    PC+2
    Fetch INST (PC)
    Execute INST (PC-1)
    Fetch INST (PC+1)
    Execute INST (PC)
    Fetch INST (PC+2)
    Execute INST (PC+1)
    Internal
    phase
    clock
    All instructions are single cycle, except for any program branches. These take two cycles since the fetch
    instruction is “ushed” from the pipeline while the new instruction is being fetched and then executed.
    Tcy0
    Tcy1
    Tcy2
    Tcy3
    Tcy4
    Tcy5
    1. MOVLW 55h
    Fetch 1
    Execute 1
    2. MOVWF PORTB
    Fetch 2
    Execute 2
    3. CALL SUB_1
    Fetch 3
    Execute 3
    4. BSF PORTA, BIT3 (Forced NOP)
    Fetch 4
    Flush
    5. Instruction @ address SUB_1
    Fetch SUB_1 Execute SUB_1
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