參數(shù)資料
型號： PIC16C622T-20I/SO
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 20 MHz, RISC MICROCONTROLLER, PDSO18
封裝： 0.300 INCH, PLASTIC, MS-013, SO-18
文件頁數(shù)： 86/128頁
文件大?。?/td> 3677K
代理商： PIC16C622T-20I/SO
PIC16C62X
DS30235J-page 58
2003 Microchip Technology Inc.
9.7
Watchdog Timer (WDT)
The Watchdog Timer is a free running on-chip RC oscil-
lator which does not require any external components.
This RC oscillator is separate from the RC oscillator of
the CLKIN pin. That means that the WDT will run, even
if the clock on the OSC1 and OSC2 pins of the device
has been stopped, for example, by execution of a
SLEEP
instruction. During normal operation, a WDT
time-out generates a device RESET. If the device is in
SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation. The WDT
can be permanently disabled by programming the
configuration bit WDTE as clear (Section 9.1).
9.7.1
WDT PERIOD
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). The time-out periods vary with tempera-
ture, V
DD and process variations from part to part (see
DC specs). If longer time-out periods are desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT under software control by writing
to the OPTION register. Thus, time-out periods up to
2.3 seconds can be realized.
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler, if assigned to the WDT, and prevent
it from timing out and generating a device RESET.
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer time-out.
9.7.2
WDT PROGRAMMING
CONSIDERATIONS
It should also be taken in account that under worst case
conditions (V
DD = Min., Temperature = Max., max.
WDT prescaler) it may take several seconds before a
WDT time-out occurs.
FIGURE 9-17:
WATCHDOG TIMER BLOCK DIAGRAM
TABLE 9-7:
SUMMARY OF WATCHDOG TIMER REGISTERS
0
M
U
X
From TMR0 Clock Source
To TMR0 (Figure 6-6)
Postscaler
Watchdog
Timer
PSA
8 - to -1 MUX
PSA
WDT
Time-out
1
0
1
WDT
Enable Bit
PS<2:0>
Note:
T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register.
8
MUX
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR Reset
Value on all
other
RESETS
2007h
Config. bits —
BODEN
CP1
CP0
PWRTE
WDTE
FOSC1
FOSC0
—
81h
OPTION
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
Legend: Shaded cells are not used by the Watchdog Timer.
Note:
_ = Unimplemented location, read as “0”
+ = Reserved for future use
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