參數(shù)資料
型號(hào)： PIC16C505
廠商： Microchip Technology Inc.
英文描述： 14-Pin, 8-Bit CMOS Microcontroller(每個(gè)I/O口有25mA驅(qū)動(dòng)/吸收電流,12個(gè)I/O口，帶WDT的微控制器)
中文描述： 14引腳，8位CMOS微控制器（每個(gè)的I / O口有25毫安驅(qū)動(dòng)/吸收電流，12個(gè)的I / O口，帶看門(mén)狗的微控制器）
文件頁(yè)數(shù)： 34/80頁(yè)
文件大?。?/td> 617K
代理商： PIC16C505
PIC16C505
DS40192A-page 34
Preliminary
1998 Microchip Technology Inc.
FIGURE 7-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO V
DD
): SLOW V
DD
RISE TIME
V
DD
MCLR
INTERNAL POR
DRT TIME-OUT
INTERNAL RESET
T
DRT
V1
When V
rises slowly, the T
time-out expires long before V
DD
has reached its final value. In
this example, the chip will reset properly if, and only if, V1
≥
V
DD
min.
7.5
Device Reset Timer (DRT)
In the PIC16C505, the DRT runs any time the device is
powered up. DRT runs from RESET and varies based
on oscillator selection (see Table 7-5.)
The Device Reset Timer (DRT) provides a fixed 18 ms
nominal time-out on reset. The DRT operates on an
internal RC oscillator. The processor is kept in RESET
as long as the DRT is active. The DRT delay allows
V
DD
to rise above V
DD
min., and for the oscillator to
stabilize.
Oscillator circuits based on crystals or ceramic
resonators require a certain time after power-up to
establish a stable oscillation. The on-chip DRT keeps
the device in a RESET condition for approximately 18
ms after MCLR has reached a logic high (V
IH
MCLR)
level. Thus, programming RB3/MCLR/V
PP
as MCLR
and using an external RC network connected to the
MCLR input is not required in most cases, allowing for
savings in cost-sensitive and/or space restricted
applications, as well as allowing the use of the RB3/
MCLR/V
PP
pin as a general purpose input.
The Device Reset time delay will vary from chip to chip
due to V
DD
, temperature, and process variation. See
AC parameters for details.
The DRT will also be triggered upon a Watchdog Timer
time-out (only in HS, XT and LP modes). This is
particularly important for applications using the WDT
to wake from SLEEP mode automatically.
7.6
Watchdog Timer (WDT)
The Watchdog Timer (WDT) is a free running on-chip
RC oscillator which does not require any external
components. This RC oscillator is separate from the
external RC oscillator of the RB5/OSC1/CLKIN pin
and the internal 4 MHz oscillator. That means that the
WDT will run even if the main processor clock has
been stopped, for example, by execution of a
SLEEP
instruction. During normal operation or SLEEP, a WDT
reset or wake-up reset generates a device RESET.
The TO bit (STATUS<4>) will be cleared upon a
Watchdog Timer reset.
The WDT can be permanently disabled by
programming the configuration bit WDTE as a '0'
(Section 7.1). Refer to the PIC16C505 Programming
Specifications to determine how to access the
configuration word.
TABLE 7-5:
DRT (DEVICE RESET TIMER
PERIOD)
Oscillator
Configuration
POR Reset
Subsequent
Resets
IntRC &
ExtRC
HS, XT & LP
18 ms (typical)
300
μ
s (typi-
cal)
18 ms (typical)
18 ms (typical)
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PIC16C505/JW 功能描述:8位微控制器 -MCU 1.5KB 72 RAM 12 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC16C505-04/P 功能描述:8位微控制器 -MCU 1.5KB 72 RAM 12 I/O 4MHz PDIP14 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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