參數(shù)資料
型號(hào): PIC12F683T-I/SN
廠商: Microchip Technology
文件頁數(shù): 57/176頁
文件大小: 0K
描述: IC PIC MCU FLASH 2KX14 8-SOIC
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
Digi-Key 應(yīng)用說明: AN0005 PWM Example with Microchip's CCP Module
AN0005 Example Code
標(biāo)準(zhǔn)包裝: 3,300
系列: PIC® 12F
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 5
程序存儲(chǔ)器容量: 3.5KB(2K x 14)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
包裝: 帶卷 (TR)
產(chǎn)品目錄頁面: 645 (CN2011-ZH PDF)
配用: AC162058-ND - HEADER MPLAB ICD2 FOR PIC12F683
I3-DB12F683-ND - BOARD DAUGHTER ICEPIC3
其它名稱: PIC12F683T-I/SN-ND
PIC12F683T-I/SNTR
2007 Microchip Technology Inc.
DS41211D-page 13
PIC12F683
3.2.2.3
INTCON Register
The INTCON register is a readable and writable
register, which contains the various enable and flag bits
for TMR0 register overflow, GPIO change and external
GP2/INT pin interrupts.
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE of the INTCON register.
User software should ensure the appropri-
ate interrupt flag bits are clear prior to
enabling an interrupt.
REGISTER 3-3:
INTCON: INTERRUPT CONTROL REGISTER
R/W-0
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
GIE: Global Interrupt Enable bit
1
= Enables all unmasked interrupts
0
= Disables all interrupts
bit 6
PEIE: Peripheral Interrupt Enable bit
1
= Enables all unmasked peripheral interrupts
0
= Disables all peripheral interrupts
bit 5
T0IE: Timer0 Overflow Interrupt Enable bit
1
= Enables the Timer0 interrupt
0
= Disables the Timer0 interrupt
bit 4
INTE: GP2/INT External Interrupt Enable bit
1
= Enables the GP2/INT external interrupt
0
= Disables the GP2/INT external interrupt
bit 3
GPIE: GPIO Change Interrupt Enable bit(1)
1
= Enables the GPIO change interrupt
0
= Disables the GPIO change interrupt
bit 2
T0IF: Timer0 Overflow Interrupt Flag bit(2)
1
= Timer0 register has overflowed (must be cleared in software)
0
= Timer0 register did not overflow
bit 1
INTF: GP2/INT External Interrupt Flag bit
1
= The GP2/INT external interrupt occurred (must be cleared in software)
0
= The GP2/INT external interrupt did not occur
bit 0
GPIF: GPIO Change Interrupt Flag bit
1
= When at least one of the GPIO <5:0> pins changed state (must be cleared in software)
0
= None of the GPIO <5:0> pins have changed state
Note 1:
IOC register must also be enabled.
2:
T0IF bit is set when TMR0 rolls over. TMR0 is unchanged on Reset and should be initialized before
clearing T0IF bit.
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