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參數(shù)資料
| 型號： | PIC12CE674-10/P |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 60/129頁 |
| 文件大小： | 0K |
| 描述： | IC MCU OTP 2KX14 A/D&EE 8DIP |
| 產(chǎn)品培訓(xùn)模塊： | Asynchronous Stimulus 8-bit PIC® Microcontroller Portfolio |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | PIC® 12C |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 10MHz |
| 外圍設(shè)備： | POR，WDT |
| 輸入/輸出數(shù)： | 5 |
| 程序存儲器容量： | 3.5KB（2K x 14） |
| 程序存儲器類型： | OTP |
| EEPROM 大?。?/td> | 16 x 8 |
| RAM 容量： | 128 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 4x8b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 8-DIP（0.300"，7.62mm） |
| 包裝： | 管件 |
| 配用： | ISPICR1-ND - ADAPTER IN-CIRCUIT PROGRAMMING AC124001-ND - MODULE SKT PROMATEII 8DIP/SOIC |
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PIC12C67X
DS30561B-page 36
1999 Microchip Technology Inc.
6.3
Write Operations
6.3.1
BYTE WRITE
Following the start signal from the processor, the
device code (4 bits), the don’t care bits (3 bits), and the
R/W bit (which is a logic low) are placed onto the bus
by the processor. This indicates to the addressed
EEPROM that a byte with a word address will follow
after it has generated an acknowledge bit during the
ninth clock cycle. Therefore, the next byte transmitted
by the processor is the word address and will be written
into the address pointer. Only the lower four address
bits are used by the device, and the upper four bits are
don’t cares. If the address byte is acknowledged, the
processor will then transmit the data word to be written
into the addressed memory location. The memory
acknowledges again and the processor generates a
stop condition. This initiates the internal write cycle,
and during this time will not generate acknowledge sig-
nals. After a byte write command, the internal address
counter will not be incremented and will point to the
same address location that was just written. If a stop bit
sequence is transmitted to the device at any point in the
write command sequence before the entire sequence
is complete, then the command will abort and no data
will be written. If more than 8 data bits are transmitted
before the stop bit sequence is sent, then the device will
clear the previously loaded byte and begin loading the
data buffer again. If more than one data byte is trans-
mitted to the device and a stop bit is sent before a full
eight data bits have been transmitted, then the write
command will abort and no data will be written. The
EEPROM memory employs a VCC threshold detector
circuit, which disables the internal erase/write logic if
the VCC is below minimum VDD. Byte write operations
must be preceded and immediately followed by a bus
not busy bus cycle where both SDA and SCL are held
high. (See Figure 6-7 for Byte Write operation.)
6.4
Acknowledge Polling
Since the EEPROM will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the processor, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the proces-
sor sending a start condition followed by the control
byte for a write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If no ACK is returned, then the start bit and control byte
must be re-sent. If the cycle is complete, then the
device will return the ACK and the processor can then
proceed with the next read or write command. (See
Figure 6-6 for flow diagram.)
FIGURE 6-6:
ACKNOWLEDGE POLLING
FLOW
FIGURE 6-7:
BYTE WRITE
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did EEPROM
Acknowledge
(ACK = 0)?
Next
Operation
NO
YES
S
P
SDA LINE
S
T
A
R
T
S
T
O
P
CONTROL
BYTE
WORD
ADDRESS
DATA
A
C
K
A
C
K
A
C
K
10
X
10
X
XX
X = Don’t Care Bit
XX
X
0
ACTIVITY
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