參數(shù)資料
型號(hào)： PIC10F206T-I/OT
廠商： Microchip Technology
文件頁數(shù)： 51/94頁
文件大小： 0K
描述： IC PIC MCU FLASH 512X12 SOT23-6
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝： 1
系列： PIC® 10F
核心處理器： PIC
芯體尺寸： 8-位
速度： 4MHz
外圍設(shè)備： POR，WDT
輸入/輸出數(shù)： 3
程序存儲(chǔ)器容量： 768B（512 x 12）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 24 x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： SOT-23-6
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面： 637 (CN2011-ZH PDF)
配用： AC162059-ND - HEADER INTRFC MPLAB ICD2 8/14PIN
XLT06SOT-ND - SOCKET TRAN ICE 6SOT W/CABLE
AC163020-ND - ADAPTER PROGRAMMER PIC10F2XX
AC164321-ND - MODULE SKT 6L PM3 SOT23
其它名稱： PIC10F206T-I/OTDKR
56
AT89/83EB5114
4311C–8051–02/08
Find Hereafter computed Time-Out value for Fosc = 12 MHz
Reset Value = XXXX XXXXb
The WDTRST register is used to reset/enable the WDT by writing 1EH then E1H in
sequence.
WatchDog Timer During
Power Down Mode and
Idle
In Power Down mode the oscillator stops, which means the WDT also stops. While in
Power Down mode the user does not need to service the WDT. There are 2 methods of
exiting Power Down mode: by a hardware reset or via a level activated external interrupt
which is enabled prior to entering Power Down mode. When Power Down is exited with
hardware reset, servicing the WDT should occur as it normally does whenever
AT8xEB5114 is reset. Exiting Power Down with an interrupt is significantly different. The
interrupt is held low long enough for the oscillator to stabilize. When the interrupt is
brought high, the interrupt is serviced. To prevent the WDT from resetting the device
while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high.
It is suggested that the WDT be reset during the interrupt service for the interrupt used
to exit Power Down.
To ensure that the WDT does not overflow within a few states of exiting of power down,
it is best to reset the WDT just before entering power down.
In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting
while in Idle mode, the user should always set up a timer that will periodically exit Idle,
service the WDT, and re-enter Idle mode.
Table 42. Time-Out Computation @12 MHz
S2
S1
S0
Time-Out for FOSC=12 MHz
0
16.38 ms
0
1
32.77 ms
0
1
0
65.54 ms
0
1
131.07 ms
1
0
262.14 ms
1
0
1
524.29 ms
1
0
1.05 s
1
2.10 s
Table 43. WDTRST Register
7
6
5
4
3
2
1
0
-
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