參數(shù)資料
型號: PI90SD1636CFCEX
廠商: Pericom
文件頁數(shù): 10/15頁
文件大?。?/td> 0K
描述: IC TXRX ETHERNET 1.25GB 64LQFP
產(chǎn)品變化通告: Copper Wire Change 26/Sept/2011
標(biāo)準(zhǔn)包裝: 1,000
類型: 收發(fā)器
驅(qū)動器/接收器數(shù): 9/9
規(guī)程: IEEE 802
電源電壓: 3.15 V ~ 3.45 V
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 帶卷 (TR)
4
PS8922B
01/05/09
PI90SD1636C
SERDES Gigabit Ethernet Transceiver
Table 2. Pin Description
Name
Pin #
Type
Description
GND_ESD
VCC_ESD
1, 14
5, 10
P
Power and ground pairs for pad ESD structure.
TX<0>
TX<1>
TX<2>
TX<3>
TX<4>
TX<5>
TX<6>
TX<7>
TX<8>
TX<9>
2
3
4
6
7
8
9
11
12
13
TTL_IN
0-bit parallel data input pins. This data should be 10b/8b encoded. The least
signicant bit is TX<0> and is transmitted rst.
GND_TXA
VCC_TXA
15
18
P
Power and ground pair for TX PLL analog circuits.
NC
16, 17,27,
48, 49
NC
No Connect
EWRAP
19
TTL_IN
Wrap Enable. This pin is active HIGH. When asserted, the high-speed serial data
are internally wrapped from the transmitter serial data output back to the receiver
data input. Also, when asserted, DOUT± are held static at logic 1. When deasserted,
DOUT± and .DIN± are active.
VCC_TXD
GND_TXD
20
21
P
Power and ground pair for TX digital circuits.
TX_CLK
22
TTL_IN
Reference clock and transmit byte clock. This is a 125 MHz system clock supplied
by the host system. On the positive edge of the clock, the input data, TX<9:0>, are
latched into the register. This clock is multiplied by 10 internally, to generate the
transmit serial bit clock.
VCC_RXD
GND_RXD
23 28,
25
P
Power and ground pair for digital circuits in the receiver portion.
EN_CDET
24
TTL_IN
Comma Detect Enable. This pin is active HIGH. When asserted, the internal byte
alignment function is turned on, to allow the clock to synchronize with the comma
character (0011111XXX). When de-asserted, the function is disabled and will not align
the clock and data. In this mode COM_DET is set to LOW.
SIG_DET
26
TTL_
OUT
Signal Detect. This pin is active HIGH. It indicates the loss of input signal on the
high-speed serial inputs, DIN±. SIG_DET is set to LOW when differential inputs are
less than 50 mV.
VCC_RX
GND_RX
29
32
P
Power and ground pair for the clock signal of the receiver portion.
RX_CLK<1>
RX_CLK<0>
30
31
TTL_
OUT
Receiver Byte Clocks. Two 180 degrees out-of-phase 62.5 MHz clock signals that are
recovered by the receiver section. The received bytes are alternately clocked by the
rising edges of these signals. The rising edge of RX_CLK<1> aligns with a comma
character when detected.
09-0001
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