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參數(shù)資料
| 型號： | PI7C8154 |
| 英文描述： | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| 中文描述： | PCI橋| 2端口PCI至PCI橋 |
| 文件頁數(shù)： | 72/115頁 |
| 文件大?。?/td> | 879K |
| 代理商： | PI7C8154 |
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PI7C8150B
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 72 of 115
July 31, 2003 – Revision 1.031
PI7C8150B parks the primary bus only when P_GNT_L is asserted, P_REQ_L is de-
asserted, and the primary PCI bus is idle. When P_GNT_L is de-asserted, PI7C8150B 3-
states the P_AD, P_CBE, and P_PAR signals on the next PCI clock cycle. If PI7C8150B is
parking the primary PCI bus and wants to initiate a transaction on that bus, then
PI7C8150B can start the transaction on the next PCI clock cycle by asserting P_FRAME_L
if P_GNT_L is still asserted.
If the internal secondary bus arbiter is enabled, the secondary bus is always parked at the
last master that used the PCI bus. That is, PI7C8150B keeps the secondary bus grant
asserted to a particular master until a new secondary bus request comes along. After reset,
PI7C8150B parks the secondary bus at itself until transactions start occurring on the
secondary bus. Offset 48h, bit 1, can be set to 1 to park the secondary bus at PI7C8150B.
By default, offset 48h, bit 1, is set to 0. If the internal arbiter is disabled, PI7C8150B parks
the secondary bus only when the reconfigured grant signal, S_REQ_L[0], is asserted and
the secondary bus is idle.
9
CLOCKS
This chapter provides information about the clocks.
9.1
PRIMARY CLOCK INPUTS
PI7C8150B implements a primary clock input for the PCI interface. The primary interface
is synchronized to the primary clock input, P_CLK, and the secondary interface is
synchronized to the secondary clock. In synchronous mode, the secondary clock is derived
internally from the primary clock, P_CLK. PI7C8150B operates at a maximum frequency
of 66 MHz (33MHz for PI7C8150B-33).
9.2
SECONDARY CLOCK OUTPUTS
PI7C8150B has 10 secondary clock outputs, S_CLKOUT[9:0] that can be used as clock
inputs for up to nine external secondary bus devices. In synchronous mode, the
S_CLKOUT[9:0] outputs are derived from P_CLK. The secondary clock edges are delayed
from P_CLK edges by a minimum of 0ns. This is the rule for using secondary clocks:
Each secondary clock output is limited to no more than one load.
9.3
ASYNCHRONOUS MODE
In asynchronous mode, the PI7C8150B can be run in the following frequency
configuration:
Primary (MHz)
25MHz to 66MHz
Secondary (MHz)
25MHz to 66MHz
相關PDF資料 |
PDF描述 |
|---|---|
| PI7C8154-33 | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150 | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150-33 | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150A | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150A-33 | PCI Bridge | 2-Port PCI-to-PCI Bridge |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8154-33 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8154ANA | 功能描述:外圍驅(qū)動器與原件 - PCI 64-Bit/66MHz 2-Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154ANAE | 功能描述:外圍驅(qū)動器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154ANAE-33 | 功能描述:外圍驅(qū)動器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154B | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT 64 BIT 66MHZ PCI TO PCI BRIDGE |
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