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參數(shù)資料
| 型號(hào)： | PI7C8154 |
| 英文描述： | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| 中文描述： | PCI橋| 2端口PCI至PCI橋 |
| 文件頁(yè)數(shù)： | 13/115頁(yè) |
| 文件大?。?/td> | 879K |
| 代理商： | PI7C8154 |
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PI7C8150B
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 13 of 115
July 31, 2003 – Revision 1.031
Name
P_IRDY_L
Pin #
82
Pin #
T10
Type
STS
Description
Primary IRDY (Active LOW).
Driven by the initiator
of a transaction to indicate its ability to complete current
data phase on the primary side. Once asserted in a data
phase, it is not de-asserted until the end of the data
phase. Before tri-stated, it is driven to a de-asserted
state for one cycle.
Primary TRDY (Active LOW).
Driven by the target
of a transaction to indicate its ability to complete current
data phase on the primary side. Once asserted in a data
phase, it is not de-asserted until the end of the data
phase. Before tri-stated, it is driven to a de-asserted state
for one cycle.
Primary Device Select (Active LOW).
Asserted by the
target indicating that the device is accepting the
transaction. As a master, PI7C8150B waits for the
assertion of this signal within 5 cycles of P_FRAME_L
assertion; otherwise, terminate with master abort. Before
tri-stated, it is driven to a de-asserted state for one cycle.
Primary STOP (Active LOW).
Asserted by the target
indicating that the target is requesting the initiator to
stop the current transaction. Before tri-stated, it is driven
to a de-asserted state for one cycle.
Primary LOCK (Active LOW).
Asserted by the
master for multiple transactions to complete.
Primary ID Select.
Used as a chip select line for Type
0 configuration access to PI7C8150B configuration
space.
Primary Parity Error (Active LOW).
Asserted when
a data parity error is detected for data received on the
primary interface. Before being tri-stated, it is driven to
a de-asserted state for one cycle.
Primary System Error (Active LOW).
Can be driven
LOW by any device to indicate a system error condition.
PI7C8150B drives this pin on:
!
Address parity error
!
Posted write data parity error on target bus
!
Secondary S_SERR_L asserted
!
Master abort during posted write transaction
!
Target abort during posted write transaction
!
Posted write transaction discarded
!
Delayed write request discarded
!
Delayed read request discarded
!
Delayed transaction master timeout
This signal requires an external pull-up resistor for
proper operation.
Primary Request (Active LOW):
This is asserted by
PI7C8150B to indicate that it wants to start a transaction
on the primary bus. PI7C8150B de-asserts this pin for at
least 2 PCI clock cycles before asserting it again.
Primary Grant (Active LOW):
When asserted,
PI7C8150B can access the primary bus. During idle and
P_GNT_L asserted, PI7C8150B will drive P_AD,
P_CBE, and P_PAR to valid logic levels.
Primary RESET (Active LOW):
When P_RESET_L is
active, all PCI signals should be asynchronously tri-
stated.
P_TRDY_L
83
R10
STS
P_DEVSEL_L
84
P10
STS
P_STOP_L
85
T11
STS
P_LOCK_L
87
R11
STS
P_IDSEL
65
P6
I
P_PERR_L
88
T12
STS
P_SERR_L
89
P11
OD
P_REQ_L
47
P2
TS
P_GNT_L
46
R1
I
P_RESET_L
43
P1
I
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C8154-33 | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150 | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150-33 | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150A | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150A-33 | PCI Bridge | 2-Port PCI-to-PCI Bridge |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8154-33 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8154ANA | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 64-Bit/66MHz 2-Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154ANAE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154ANAE-33 | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154B | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT 64 BIT 66MHZ PCI TO PCI BRIDGE |
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