<thead id="uyyxr"></thead>
  • <big id="uyyxr"><sup id="uyyxr"></sup></big><nobr id="uyyxr"><small id="uyyxr"><nobr id="uyyxr"></nobr></small></nobr>
    參數(shù)資料
    型號: PI7C8150A
    英文描述: PCI Bridge | 2-Port PCI-to-PCI Bridge
    中文描述: PCI橋| 2端口PCI至PCI橋
    文件頁數(shù): 95/115頁
    文件大?。?/td> 879K
    代理商: PI7C8150A
    PI7C8150B
    2-PORT PCI-TO-PCI BRIDGE
    ADVANCE INFORMATION
    Page 95 of 115
    July 31, 2003 – Revision 1.031
    14.1.39
    GPIO DATA AND CONTROL REGISTER – OFFSET 64h
    Bit
    Function
    Type
    Description
    Writing 1 to any of these bits drives the corresponding bit LOW on
    the GPIO[3:0] bus if it is programmed as bidirectional. Data is
    driven on the PCI clock cycle following completion of the
    configuration write to this register. Bit positions corresponding to
    GPIO pins that are programmed as input only are not driven. Writing
    0 has no effect and will show last the last value written when read.
    Reset to 0.
    Writing 1 to any of these bits drives the corresponding bit HIGH on
    the GPIO[3:0] bus if it is programmed as bidirectional. Data is
    driven on the PCI clock cycle following completion of the
    configuration write to this register. Bit positions corresponding to
    GPIO pins that are programmed as input only are not driven. Writing
    0 has no effect and will show last the last value written when read.
    Reset to 0.
    Writing 1 to and of these bits configures the corresponding
    GPIO[3:0] pin as an input only. The output driver is tristated.
    Writing 0 to this register has no effect and will reflect the last value
    written when read.
    Reset to 0.
    Writing 1 to and of these bits configures the corresponding
    GPIO[3:0] pin as bidirectional. The output driver is enabled and
    drives the value set in the output data register (65h). Writing 0 to this
    register has no effect and will reflect the last value written when read.
    Reset to 0.
    Reserved. Returns 0 when read. Reset to 0.
    Reads the state of the GPIO[3:0] pins. The state is updated on the PCI
    clock following a change in the GPIO[3:0] pins.
    11:8
    GPIO Output
    Write-1-to-Clear
    R/WC
    15:12
    GPIO Output
    Write-1-to-Set
    R/WS
    19:16
    GPIO Output
    Enable Write-1-
    to-Clear
    R/WC
    23:20
    GPIO Output
    Enable Write-1-
    to-Set
    R/WS
    27:24
    Reserved
    GPIO Input Data
    Register
    R
    31:28
    R/O
    14.1.40
    SECONDARY CLOCK CONTROL REGISTER – OFFSET 68h
    Bit
    Function
    Type
    Description
    If either bit is 0, then S_CLKOUT [0] is enabled.
    If both bits are 1, then S_CLKOUT [0] is disabled.
    If either bit is 0, then S_CLKOUT [1] is enabled.
    If both bits are 1, then S_CLKOUT [1] is disabled.
    If either bit is 0, then S_CLKOUT [2] is enabled.
    If both bits are 1, then S_CLKOUT [2] is disabled.
    If either bit is 0, then S_CLKOUT [3] is enabled.
    If both bits are 1, then S_CLKOUT [3] is disabled.
    If bit is 0, then S_CLKOUT [4] is enabled.
    If bit is 1, then S_CLKOUT [4] is disabled and driven low.
    If bit is 0, then S_CLKOUT [5] is enabled.
    If bit is 1, then S_CLKOUT [5] is disabled and driven low.
    If bit is 0, then S_CLKOUT [6] is enabled.
    If bit is 1, then S_CLKOUT [6] is disabled and driven low.
    If bit is 0, then S_CLKOUT [7] is enabled.
    If bit is 1, then S_CLKOUT [7] is disabled and driven low.
    If bit is 0, then S_CLKOUT [8] is enabled.
    If bit is 1, then S_CLKOUT [8] is disabled and driven low.
    If bit is 0, then S_CLKOUT [9] is enabled.
    If bit is 1, then S_CLKOUT [9] is disabled and driven low.
    Reserved. Returns 00 when read.
    1:0
    Clock 0 disable
    R/W
    3:2
    Clock 1 disable
    R/W
    5:4
    Clock 2 disable
    R/W
    7:6
    Clock 3 disable
    R/W
    8
    Clock 4 disable
    R/W
    9
    Clock 5 disable
    R/W
    10
    Clock 6 disable
    R/W
    11
    Clock 7 disable
    R/W
    12
    Clock 8 disable
    R/W
    13
    Clock 9 disable
    R/W
    15:14
    Reserved
    RO
    相關(guān)PDF資料
    PDF描述
    PI7C8150A-33 PCI Bridge | 2-Port PCI-to-PCI Bridge
    PI7C8150B PCI Bridge | Asynchronous 2-Port PCI Bridge
    PI7C8152A ENHANCED 2- PORT TO PCI BRIDGE INTEL 21152 COMPORISON
    PI7C81552 ENHANCED 2-PORT PCI TO PCI BRIDGE INTEL 21152 COMPARISON
    PI7C81552A ENHANCED 2-PORT PCI TO PCI BRIDGE INTEL 21152 COMPARISON
    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
    PI7C8150A-33 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | 2-Port PCI-to-PCI Bridge
    PI7C8150AMA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 208-Pin FQFP
    PI7C8150AMA-33 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 208-Pin FQFP
    PI7C8150AMAE 功能描述:外圍驅(qū)動器與原件 - PCI 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
    PI7C8150AMAE-33 功能描述:外圍驅(qū)動器與原件 - PCI 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray