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參數(shù)資料
| 型號(hào)： | PI7C8150A |
| 英文描述： | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| 中文描述： | PCI橋| 2端口PCI至PCI橋 |
| 文件頁(yè)數(shù)： | 27/115頁(yè) |
| 文件大?。?/td> | 879K |
| 代理商： | PI7C8150A |
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PI7C8150B
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 27 of 115
July 31, 2003 – Revision 1.031
in data buffers at the same time. See Chapter 6 for information about how multiple posted
and delayed write transactions are ordered.
3.5.6
FAST BACK-TO-BACK TRANSACTIONS
PI7C8150B can recognize and post fast back-to-back write transactions.
When PI7C8150B cannot accept the second transaction because of buffer
space limitations, it returns a target retry to the initiator. The fast back-to-back enable bit
must be set in the command register for upstream write transactions, and in the bridge
control register for downstream write transactions.
3.6
READ TRANSACTIONS
Delayed read forwarding is used for all read transactions crossing PI7C8150B. Delayed
read transactions are treated as either prefetchable or non-prefetchable. Table 3-5 shows the
read behavior, prefetchable or non-prefetchable, for each type of read operation.
3.6.1
PREFETCHABLE READ TRANSACTIONS
A prefetchable read transaction is a read transaction where PI7C8150B performs
speculative DWORD reads, transferring data from the target before it is requested from the
initiator. This behavior allows a prefetchable read transaction to consist of multiple data
transfers. However, byte enable bits cannot be forwarded for all data phases as is done for
the single data phase of the non-prefetchable read transaction. For prefetchable read
transactions, PI7C8150B forces all byte enable bits to be turned on for all data phases.
Prefetchable behavior is used for memory read line and memory read multiple transactions,
as well as for memory read transactions that fall into prefetchable memory space.
The amount of data that is pre-fetched depends on the type of transaction. The amount of
pre-fetching may also be affected by the amount of free buffer space available in
PI7C8150B, and by any read address boundaries encountered.
Pre-fetching should not be used for those read transactions that have side effects in the
target device, that is, control and status registers, FIFO’s, and so on. The target device’s
base address register or registers indicate if a memory address region is prefetchable.
3.6.2
NON-PREFETCHABLE READ TRANSACTIONS
A non-prefetchable read transaction is a read transaction where PI7C8150B requests one
and only one DWORD from the target and disconnects the initiator after delivery of the
first DWORD of read data. Unlike prefetchable read transactions, PI7C8150B forwards the
read byte enable information for the data phase.
Non-prefetchable behavior is used for I/O and configuration read transactions, as well as
for memory read transactions that fall into non-prefetchable memory space.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C8150A-33 | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150B | PCI Bridge | Asynchronous 2-Port PCI Bridge |
| PI7C8152A | ENHANCED 2- PORT TO PCI BRIDGE INTEL 21152 COMPORISON |
| PI7C81552 | ENHANCED 2-PORT PCI TO PCI BRIDGE INTEL 21152 COMPARISON |
| PI7C81552A | ENHANCED 2-PORT PCI TO PCI BRIDGE INTEL 21152 COMPARISON |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8150A-33 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150AMA | 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 208-Pin FQFP |
| PI7C8150AMA-33 | 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 208-Pin FQFP |
| PI7C8150AMAE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8150AMAE-33 | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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