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參數(shù)資料
| 型號： | PI7C8150-33 |
| 英文描述： | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| 中文描述： | PCI橋| 2端口PCI至PCI橋 |
| 文件頁數(shù)： | 66/115頁 |
| 文件大小： | 879K |
| 代理商： | PI7C8150-33 |
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PI7C8150B
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 66 of 115
July 31, 2003 – Revision 1.031
!
!
Master abort detected during posted write transaction
Posted write data discarded after 2
24
(default) attempts to deliver (2
24
target retries
received)
!
Parity error reported on target bus during posted write transaction (see previous
section)
!
Delayed write data discarded after 2
24
(default) attempts to deliver (2
24
target retries
received)
!
Delayed read data cannot be transferred from target after 2
24
(default) attempts (2
24
target retries received)
!
The device-specific P_SERR_L status register reports the reason for the assertion of
P_SERR_L. Most of these events have additional device-specific disable bits in the
P_SERR_L event disable register that make it possible to mask out P_SERR_L assertion
for specific events. The master timeout condition has a SERR_L enable bit for that event in
the bridge control register and therefore does not have a device-specific disable bit.
Master timeout on delayed transaction
7
EXCLUSIVE ACCESS
This chapter describes the use of the LOCK_L signal to implement exclusive access to a
target for transactions that cross PI7C8150B.
7.1
CONCURRENT LOCKS
The primary and secondary bus lock mechanisms operate concurrently except when
a locked transaction crosses PI7C8150B. A primary master can lock a primary target
without affecting the status of the lock on the secondary bus, and vice versa. This means
that a primary master can lock a primary target at the same time that a secondary master
locks a secondary target.
7.2
ACQUIRING EXCLUSIVE ACCESS ACROSS PI7C8150B
For any PCI bus, before acquiring access to the LOCK_L signal and starting a series of
locked transactions, the initiator must first check that both of the following conditions are
met:
!
The PCI bus must be idle.
!
The LOCK_L signal must be de-asserted.
The initiator leaves the LOCK_L signal de-asserted during the address phase and asserts
LOCK_L one clock cycle later. Once a data transfer is completed from the target, the target
lock has been achieved.
相關PDF資料 |
PDF描述 |
|---|---|
| PI7C8150A | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150A-33 | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150B | PCI Bridge | Asynchronous 2-Port PCI Bridge |
| PI7C8152A | ENHANCED 2- PORT TO PCI BRIDGE INTEL 21152 COMPORISON |
| PI7C81552 | ENHANCED 2-PORT PCI TO PCI BRIDGE INTEL 21152 COMPARISON |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8150A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150A-33 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150AMA | 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 208-Pin FQFP |
| PI7C8150AMA-33 | 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 208-Pin FQFP |
| PI7C8150AMAE | 功能描述:外圍驅動器與原件 - PCI 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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