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參數(shù)資料
| 型號(hào)： | PI74ALVCH16260A |
| 廠商： | Pericom |
| 文件頁(yè)數(shù)： | 1/6頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC 12/14-BIT MUX/LATCH 56-TSSOP |
| 產(chǎn)品變化通告： | Product Discontinuation 17/Feb/2006 |
| 標(biāo)準(zhǔn)包裝： | 35 |
| 系列： | 74ALVCH |
| 邏輯類型： | D 型，可尋址 |
| 電路： | 12:24 |
| 輸出類型： | 三態(tài) |
| 電源電壓： | 2.3 V ~ 3.6 V |
| 獨(dú)立電路： | 1 |
| 延遲時(shí)間 - 傳輸： | 1ns |
| 輸出電流高，低： | 24mA，24mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-TFSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 56-TSSOP |
| 包裝： | 管件 |
1
PS8089D
05/24/06
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12-Bit To 24-Bit Multiplexed D-Type Latch
with 3-State Outputs
Logic Block Diagram
G1
OE2B
C1
1D
1B1
TO 11 OTHER CHANNELS
OE1B
OEA
A1
LE1B
LE2B
LEA1B
LEA2B
SEL
1
C1
1D
C1
1D
C1
1D
2B1
23
6
28
8
1
29
56
55
30
27
2
Product Features
PI74ALVCH16260 is designed for low voltage operation
VCC = 2.3V to 3.6V
Hysteresis on all inputs
Typical VOLP (Output Ground Bounce)
< 0.8V at VCC = 3.3V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
< 2.0V at VCC = 3.3V, TA = 25°C
Bus Hold retains last active bus state during 3-State,
eliminating the need for external pullup resistors
Industrial operation at –40°C to +85°C
Packages available:
– 56-pin 240 mil wide plastic TSSOP (A)
PI74ALVCH16260
Product Description
ThePI74ALVCH16260isa12-bitto24-bitmultiplexedD-typelatch
designed for 2.3V to 3.6 VCC operation. It is used in applications
where two separate datapaths must be multiplexed onto, or
demultiplexed from, a single data path.
Typical applications include multiplexing and/or demultiplexing
address and data information in microprocessor or bus-interface
and in memory-interleaving.
Three12-bitI/Oports(A1-A12,1B1-1B12,and2B1-2B12)areavailable
for address and/or data transfer. The output-enable (OE1B, OE2B,
and OEA) inputs control bus transceiver functions. The OE1B and
OE2BcontrolsignalsalsoallowbankcontrolintheA-to-Bdirection.
Address and/or data information can be stored using the internal
storagelatches.Thelatch-enable(LE1B,LE2B,LEA1B,andLEA2B)
inputs are used to control data storage. When the latch-enable input
is HIGH, the latch is transparent. When the latch-enable input goes
LOW, the data present at the inputs is latched and remains latched
until the latch-enable input is returned HIGH.
To ensure high-impedance state during power up or power down,
OE should be tied to VCC through a pullup resistor whose minimum
value is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
06-0132
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