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參數(shù)資料
| 型號： | PI74ALVCH16721A |
| 廠商： | Pericom |
| 文件頁數(shù)： | 1/5頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 20-BIT FLIP-FLOP 56-TSSOP |
| 產(chǎn)品變化通告： | Product Discontinuation 17/Feb/2006 |
| 標準包裝： | 35 |
| 系列： | 74ALVCH |
| 功能： | 標準 |
| 類型： | D 型總線 |
| 輸出類型： | 三態(tài)非反相 |
| 元件數(shù)： | 1 |
| 每個元件的位元數(shù)： | 20 |
| 頻率 - 時鐘： | 150MHz |
| 延遲時間 - 傳輸： | 4.3ns |
| 觸發(fā)器類型： | 正邊沿 |
| 輸出電流高，低： | 24mA，24mA |
| 電源電壓： | 2.3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-TFSOP（0.240"，6.10mm 寬） |
| 包裝： | 管件 |
1
PS8090C 02/07/00
Product Description
Pericom Semiconductors PI74ALVCH series of logic circuits are
produced in the Companys advanced 0.5 micron CMOS
technology, achieving industry leading speed.
The PI74ALVCH16721 is a 20-bit flip-flop with 3-state outputs
designed specifically for 2.3V to 3.6V VCC operation. The
PI74ALVCH16721 is designed with edge-triggered D-type flip-
flops with qualified clock storage. On the positive transition of
clock (CLK) input, the device provides true data at the Q outputs,
provided that the clock-enable (CLKEN) input is LOW. If CLKEN
is HIGH, no data is stored.
A buffered output-enable (OE) input can be used to place the
20 outputs in either a normal logic state (HIGH or LOW level) or
a high-impedance state. In the high-impedance state, the outputs
neitherloadnordrivethebuslinessignificantly.Thehigh-impedance
state and increased drive provide the capacity to drive bus lines
without the need for interface or pullup components. OE does not
affect the internal operation of the flip-flops. Old data can be
retained or new data can be entered while the outputs are in the
high-impedance state.
To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
The PI74ALVCH16721 data has Bus Hold which retains the
data inputs last state whenever the data input goes to high-
impedance preventing floating inputs and eliminating the need
for pullup/down resistors.
Product Features
PI74ALVCH16721 is designed for low voltage operation
VCC = 2.3V to 3.6V
Hysteresis on all inputs
Typical VOLP (Output Ground Bounce)
< 0.8V at VCC = 3.3V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
< 2.0V at VCC = 3.3V, TA = 25°C
Bus Hold retains last active bus state during 3-STATE,
eliminating the need for external pullup resistors
Industrial operation at 40°C to +85°C
Packages available:
56-pin 240 mil wide plastic TSSOP (A)
56-pin 300 mil wide plastic SSOP (V)
Logic Block Diagram
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56
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12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
3.3V 20-Bit Flip-Flop
with 3-STATE Outputs
PI74ALVCH16721
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI74ALVCH16721V | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:20-Bit D-Type Flip-Flop |
| PI74ALVCH16820 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic | 10-Bit Flip-Flop w/Dual Outputs |
| PI74ALVCH16820A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10-Bit D-Type Flip-Flop |
| PI74ALVCH16820V | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10-Bit D-Type Flip-Flop |
| PI74ALVCH16821 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic | 20-Bit Bus Interface Flip-Flop |
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