參數(shù)資料
型號: PI2EQX4432DZDEX
廠商: Pericom
文件頁數(shù): 1/6頁
文件大?。?/td> 0K
描述: IC PCI-E REPEATER/EQUALR 48TQFN
標(biāo)準(zhǔn)包裝: 3,000
系列: *
1
PS8888A
04/26/07
Features
Two High Speed PCI Express lanes
Supports PCI Express data rates (2.5 Gbps) on each lane
Adjustable Receiver Equalization
Input Signal Level Detect & Output Squelch on all Channels
Output De-emphasis = -3.5dB
100–Ohm Differential CML I/O’s
Low Power (100mW per Channel)
Standby Mode – Power Down State
VDD Operating Range: 1.8V +/-0.1V
Packaging (Pb-free & Green): 48-contact TQFN
Description
Pericom Semiconductor’s PI2EQX4432D is a low power,
PCI Express compliant signal Re-Driver. The device provides
programmable equalization, to optimize performance by reducing
Inter-Symbol Interference (ISI). PI2EQX4432D supports two
100
Ohm Differential CML data I/O’s between the Protocol
ASIC to a switch fabric, across a backplane, or extends the signals
across other distant data pathways on the user’s platform.
The integrated equalization circuitry provides exibility with
signal integrity of the PCI Express signal before the Re-Driver.
Whereas the integrated de-emphasis circuitry provides exibility
with signal integrity of the PCI Express signal after the Re-
Driver.
A low-level input signal detection and output squelch function
is provided for all four channels. Each channel operates fully
independantly. When a channel is enabled (EN_x=1) and
operating, that channels input signal level (on xl+/-) determines
whether the output is enabled. If the input level of the channel
falls below the active threshold level (Vth-) then the output driver
switches off, and the pin is pulled to VDD via a high impedance
resistor.
In addition to providing serial re-conditioning, Pericom's
PIEQX4432D also provides a power management Stand-by mode
operated by the enable pins.
PI2EQX4432D
2.5 Gbps x2 Lane PCI Express Repeater/Equalizer
with Signal Detect and Flow-Through Pinout
Block Diagram
Pin Description (Top View)
GND
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 1718 19 20 21 22 23 24
36
35
34
33
32
31
30
29
28
27
26
25
48 47 46 45 4443 42 41 40 39 38 37
AI+
AI–
VDD
BO+
BO–
VDD
CI+
CI–
VDD
DO+
DO–
VDD
AO+
AO–
VDD
BI+
BI–
VDD
CO+
CO–
VDD
DI+
DI–
GND
VDD
SEL–EQ_A
SEL–EQ_B
SEL–OL_A
SEL–OL_B
SEL–DE_A
SEL–DE_B
EN_A
EN_B
EN_C
EN_D
VDD
EN_CLK
CLK+
CLK–
SEL–EQ_C
SEL–EQ_D
SEL–OL_C
SEL–OL_D
SEL–DE_C
SEL–DE_D
CLKO+
CLKO–
IREF
Signal Detect
CML
xO+
xO–
xl+
xl–
Equalizer
Limiting
Amp
SEL–EQ_x
SEL–OL_x
SEL–DE_x
– – Repeat 4 Times ––
CLK+
CLK–
Buffer
IREF
CLKO+
CLKO–
EN_X
Power
Management
EN_CLK
Clock
07-0106
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