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參數(shù)資料
| 型號： | PHN70308/T3 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 小信號晶體管 |
| 英文描述： | 5000 mA, 25 V, 7 CHANNEL, N-CHANNEL, Si, SMALL SIGNAL, MOSFET, MO-150AH |
| 封裝： | PLASTIC, SSOP-28 |
| 文件頁數(shù)： | 2/10頁 |
| 文件大小： | 132K |
| 代理商： | PHN70308/T3 |
NJU7706/07
- 10 -
Ver.2007-08-03
Functional Description
(1) Basic operation
(*8): C-MOS output product (NJU7707) : When VDD less than VOPL, VOUT is free of the shaded region.
(2) Description of Manual Reset
Reset signal can output independently with MR.
Logic of MR
Operation
Active "L"
VMR= "L" => Reset "ON"
Active "H"
VMR= "H" => Reset "ON"
If Manual Reset is not required, please connect MR terminal as following.
Logic of MR
Connection
Active "L"
Connect MR terminal to VDD or open
Active "H"
Connect MR terminal to GND or open
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
(1) When supply voltage(VDD) drops below
detection voltage(VDET), Output voltage(VOUT)
changes "H" to "L" to alert reset state.
(2) The reset state is kept while VDD is lower than
release voltage. The release voltage is a sum
of VDET and Hysterisis voltage (VHYS). Please
refer to the (*7) below.
(3) When VDD becomes higher than the release
voltage and reset release delay time fixed by
internal is past, then VOUT changes from "L" to
"H" to resume normal state.
(*7) VHYS is to avoid unstable VOUT state caused
by rapid voltage change at nearby VDET.
Detection voltage
(VDET)
Release voltage
(VDET+ VHYS)
Hysteresis voltage
(VHYS)
Supply voltage
(VDD)
Output voltage
(VOUT)
Minimum operation
voltage (VOPL)
VSS
Delay time
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