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參數(shù)資料
| 型號： | PHD87N03LT |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | JFETs |
| 英文描述： | N-channel TrenchMOS transistor Logic level FET(N溝道TrenchMOS 晶體管邏輯電平場效應(yīng)管) |
| 中文描述： | 75 A, 25 V, 0.0105 ohm, N-CHANNEL, Si, POWER, MOSFET |
| 封裝： | PLASTIC, DPAK-3 |
| 文件頁數(shù)： | 3/11頁 |
| 文件大?。?/td> | 99K |
| 代理商： | PHD87N03LT |
Philips Semiconductors
Product specification
N-channel TrenchMOS
transistor
Logic level FET
PHP87N03LT, PHB87N03LT
PHD87N03LT
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= 25C unless otherwise specified
SYMBOL PARAMETER
I
S
Continuous source current
(body diode)
I
SM
Pulsed source current (body
diode)
V
SD
Diode forward voltage
CONDITIONS
MIN.
-
TYP. MAX. UNIT
-
75
A
-
-
240
A
I
F
= 25 A; V
GS
= 0 V
I
F
= 40 A; V
GS
= 0 V
I
F
= 20 A; -dI
F
/dt = 100 A/
μ
s;
V
GS
= 0 V; V
R
= 25 V
-
-
-
-
0.85
0.9
109
0.2
1.2
-
-
-
V
t
rr
Q
rr
Reverse recovery time
Reverse recovery charge
ns
μ
C
Fig.1. Normalised power dissipation.
PD% = 100
P
D
/P
D 25 C
= f(T
mb
)
Fig.2. Normalised continuous drain current.
ID% = 100
I
D
/I
D 25 C
= f(T
mb
); V
GS
≥
5 V
Fig.3. Safe operating area
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Fig.4. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
Normalised Power Derating, PD (%)
0
10
20
30
40
50
60
70
80
90
100
0
25
50
75
100
125
150
175
Mounting Base temperature, Tmb (C)
1
10
100
1000
1
100
Drain-Source 10
Peak Pulsed Drain Current, IDM (A)
D.C.
100 ms
10 ms
RDS(on) = VDS/ ID
1 ms
tp = 10 us
100 us
Normalised Current Derating, ID (%)
0
10
20
30
40
50
60
70
80
90
100
0
25
50
75
100
125
150
175
Mounting Base temperature, Tmb (C)
0.01
0.1
1
10
1E-06
1E-05
1E-04
1E-03
1E-02
1E-01
1E+00
Pulse width, tp (s)
Transient thermal impedance, Zth j-mb (K/W)
single pulse
D = 0.5
0.2
0.1
0.05
0.02
tp
D = tp/T
D
P
T
October 1999
3
Rev 1.600
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