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參數(shù)資料
| 型號： | PHD69N03LT |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | JFETs |
| 英文描述： | N-channel TrenchMOS transistor Logic level FET(N溝道TrenchMOS 晶體管邏輯電平場效應管) |
| 中文描述： | 69 A, 25 V, 0.014 ohm, N-CHANNEL, Si, POWER, MOSFET |
| 封裝： | PLASTIC, DPAK-3 |
| 文件頁數(shù)： | 2/11頁 |
| 文件大小： | 108K |
| 代理商： | PHD69N03LT |
Philips Semiconductors
Product specification
N-channel TrenchMOS
transistor
Logic level FET
PHP69N03LT, PHB69N03LTT
PHD69N03LT
THERMAL RESISTANCES
SYMBOL PARAMETER
R
th j-mb
Thermal resistance junction
to mounting base
R
th j-a
Thermal resistance junction
to ambient
CONDITIONS
MIN.
-
TYP. MAX. UNIT
-
1.2
K/W
SOT78 package, in free air
SOT404 and SOT428 packages, pcb
mounted, minimum footprint
-
-
60
50
-
-
K/W
K/W
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
W
DSS
Drain-source non-repetitive
unclamped inductive turn-off
energy
CONDITIONS
I
D
= 25 A; V
DD
≤
15 V;
V
GS
= 5 V; R
GS
= 50
; T
mb
= 25 C
MIN.
-
MAX.
60
UNIT
mJ
ELECTRICAL CHARACTERISTICS
T
j
= 25C unless otherwise specified
SYMBOL PARAMETER
V
(BR)DSS
Drain-source breakdown
voltage
V
GS(TO)
Gate threshold voltage
CONDITIONS
V
GS
= 0 V; I
D
= 0.25 mA;
MIN.
25
22
1
0.5
-
-
-
-
12
-
-
-
-
-
-
-
-
-
-
TYP. MAX. UNIT
-
-
-
-
1.5
2
-
-
-
2.3
8.5
12
11
14
-
26
40
-
10
100
0.05
10
-
500
26
-
7.6
-
11
-
7
15
50
75
82
120
59
75
V
V
V
V
V
T
j
= -55C
V
DS
= V
GS
; I
D
= 1 mA
T
j
= 175C
T
j
= -55C
R
DS(ON)
Drain-source on-state
resistance
V
GS
= 10 V; I
= 25 A
V
GS
= 5 V; I
D
= 25 A
V
GS
= 5 V; I
D
= 25 A; T
j
= 175C
V
DS
= 25 V; I
D
= 25 A
m
m
m
S
nA
μ
A
μ
A
nC
nC
nC
ns
ns
ns
ns
g
fs
I
GSS
I
DSS
Forward transconductance
Gate source leakage current V
GS
=
±
5 V; V
DS
= 0 V
Zero gate voltage drain
current
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
V
DS
= 25 V; V
GS
= 0 V;
T
j
= 175C
Q
g(tot)
Q
gs
Q
gd
t
d on
t
r
t
d off
t
f
L
d
L
d
I
D
= 69 A; V
DD
= 15 V; V
GS
= 5 V
V
DD
= 15 V; I
D
= 25 A;
V
= 10 V; R
G
= 5
Resistive load
Internal drain inductance
Internal drain inductance
Measured tab to centre of die
Measured from drain lead to centre of die
(SOT78 package only)
Measured from source lead to source
bond pad
V
GS
= 0 V; V
DS
= 20 V; f = 1 MHz
-
-
3.5
4.5
-
-
nH
nH
L
s
Internal source inductance
-
7.5
-
nH
C
iss
C
oss
C
rss
Input capacitance
Output capacitance
Feedback capacitance
-
-
-
1700
475
300
-
-
-
pF
pF
pF
October 1999
2
Rev 1.600
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|---|---|
| PHP69N03LT | N-channel TrenchMOS transistor Logic level FET(N溝道TrenchMOS 晶體管邏輯電平場效應管) |
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| PHB80N06LT | TrenchMOS transistor Logic level FET |
| PHB80N06T | TrenchMOS transistor Standard level FET |
| PHB87N03LT | N-channel TrenchMOS transistor Logic level FET(N溝道TrenchMOS 晶體管邏輯電平場效應管) |
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