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參數(shù)資料
| 型號： | PHB69N03T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | JFETs |
| 英文描述： | TrenchMOS transistor Standard Level FET(TrenchMOS 晶體管標(biāo)準(zhǔn)電平場效應(yīng)管) |
| 中文描述： | 69 A, 30 V, 0.014 ohm, N-CHANNEL, Si, POWER, MOSFET |
| 封裝： | PLASTIC PACKAGE-3 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大小： | 66K |
| 代理商： | PHB69N03T |
Philips Semiconductors
Product specification
TrenchMOS
transistor
Standard level FET
PHB69N03T
GENERAL DESCRIPTION
QUICK REFERENCE DATA
N-channel
standard level field-effect power
transistor
in
a
suitable for surface mounting using
’
trench
’ technology.
featuresverylow on-state resistance
and has integral zener diodes giving
ESD protection up to 2kV. It is
intended
for
use
converters and
switching applications.
enhancement
mode
SYMBOL
PARAMETER
MAX.
UNIT
plastic envelope
V
DS
I
D
P
tot
T
j
R
DS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance
30
69
125
175
14
V
A
W
C
m
The
device
V
GS
= 10 V
in
DC-DC
general purpose
PINNING - SOT404
PIN CONFIGURATION
SYMBOL
PIN
DESCRIPTION
1
gate
2
drain
3
source
mb
drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
V
DS
V
DGR
±
V
GS
I
D
I
D
I
DM
P
tot
T
stg
, T
j
PARAMETER
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage & operating temperature
CONDITIONS
-
R
GS
= 20 k
-
T
mb
= 25 C
T
mb
= 100 C
T
mb
= 25 C
T
mb
= 25 C
-
MIN.
-
-
-
-
-
-
-
- 55
MAX.
30
30
20
69
48
240
125
175
UNIT
V
V
V
A
A
A
W
C
THERMAL RESISTANCES
SYMBOL
R
th j-mb
PARAMETER
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
CONDITIONS
-
TYP.
-
MAX.
1.2
UNIT
K/W
R
th j-a
minimum footprint, FR4
board
50
-
K/W
ESD LIMITING VALUE
SYMBOL
V
C
PARAMETER
Electrostatic discharge capacitor
voltage, all pins
CONDITIONS
Human body model
(100 pF, 1.5 k
)
MIN.
-
MAX.
2
UNIT
kV
d
g
s
1
3
mb
2
December 1997
1
Rev 1.200
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