- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄367934 > PH28F640L18B85 (INTEL CORP) StrataFlash Wireless Memory PDF資料下載
參數(shù)資料
| 型號： | PH28F640L18B85 |
| 廠商： | INTEL CORP |
| 元件分類： | PROM |
| 英文描述： | StrataFlash Wireless Memory |
| 中文描述： | 4M X 16 FLASH 1.8V PROM, 85 ns, PBGA56 |
| 封裝： | 0.75 MM PITCH, LEAD FREE, VFBGA-56 |
| 文件頁數(shù)： | 50/106頁 |
| 文件大?。?/td> | 1272K |
| 代理商： | PH28F640L18B85 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁當(dāng)前第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁
Intel StrataFlash Wireless Memory (L18)
April 2005
50
Intel StrataFlash Wireless Memory (L18)
Order Number: 251902, Revision: 009
Datasheet
10.0
Read Operations
The device supports two read modes: asynchronous page mode and synchronous burst mode.
Asynchronous page mode is the default read mode after device power-up or a reset. The Read
Configuration Register must be configured to enable synchronous burst reads of the flash memory
array (see
Section 10.3, “Read Configuration Register (RCR)” on page 51
).
Each partition of the device can be in any of four read states: Read Array, Read Identifier, Read
Status or Read Query. Upon power-up, or after a reset, all partitions of the device default to Read
Array. To change a partition’s read state, the appropriate read command must be written to the
device (see
Section 9.2, “Device Commands” on page 47
). See
Section 15.0, “Special Read States”
on page 75
for details regarding Read Status, Read ID, and CFI Query modes.
The following sections describe read-mode operations in detail.
10.1
Asynchronous Page-Mode Read
Following a device power-up or reset, asynchronous page mode is the default read mode and all
partitions are set to Read Array. However, to perform array reads after any other device operation
(e.g. write operation), the Read Array command must be issued in order to read from the flash
memory array.
Note:
Asynchronous page-mode reads can only be performed when Read Configuration Register bit
RCR[15] is set (see
Section 10.3, “Read Configuration Register (RCR)” on page 51
).
To perform an asynchronous page-mode read, an address is driven onto A[MAX:0], and CE# and
ADV# are asserted. WE# and RST# must already have been deasserted. WAIT is deasserted during
asynchronous page mode. ADV# can be driven high to latch the address, or it must be held low
throughout the read cycle. CLK is not used for asynchronous page-mode reads, and is ignored. If
only asynchronous reads are to be performed, CLK should be tied to a valid V
IH
level, WAIT
signal can be floated and ADV# must be tied to ground. Array data is driven onto DQ[15:0] after
an initial access time t
AVQV
delay. (see
Section 7.0, “AC Characteristics” on page 28
).
In asynchronous page mode, four data words are “sensed” simultaneously from the flash memory
array and loaded into an internal page buffer. The buffer word corresponding to the initial address
on A[MAX:0] is driven onto DQ[15:0] after the initial access delay. Address bits A[MAX:2] select
the 4-word page. Address bits A[1:0] determine which word of the 4-word page is output from the
data buffer at any given time.
10.2
Synchronous Burst-Mode Read
Section 10.3, “Read Configuration Register (RCR)” on page 51
continuous-wordsTo perform a
synchronous burst- read, an initial address is driven onto A[MAX:0], and CE# and ADV# are
asserted. WE# and RST# must already have been deasserted. ADV# is asserted, and then
deasserted to latch the address. Alternately, ADV# can remain asserted throughout the burst access,
in which case the address is latched on the next valid CLK edge while ADV# is asserted.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PH28F640L18T85 | StrataFlash Wireless Memory |
| PH2907A | PNP switching transistor |
| PH2907 | PNP switching transistor |
| PH2931-135S | Rail-to-Rail, Very Low Noise Universal Dual Filter Building Block; Package: SO; No of Pins: 16; Temperature Range: -40°C to +85°C |
| PH2931-I3 | Radar Pulsed Power Transistor, 135W, 20ms Pulse, 1% Duty 2.9 - 3.1 GHz |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PH28F640L18T85 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:StrataFlash Wireless Memory |
| PH28F640W18BD60 | 制造商:Micron Technology Inc 功能描述:PH28F640W18BD60S L785 |
| PH28F640W18BD60B | 制造商:Micron Technology Inc 功能描述:NUMPH28F640W18BD60B PH28F640W18BD60S L78 |
| PH28F640W18TE60B | 制造商:Micron Technology Inc 功能描述:64MB, CRYSTAL .75 VFBGA 1.8 LF - Tape and Reel |
| PH28F640W30BD70A | 制造商:Micron Technology Inc 功能描述:NOR Flash Parallel/Serial 1.8V 64Mbit 4M x 16bit 70ns 56-Pin VFBGA Tray 制造商:Micron Technology Inc 功能描述:NUMPH28F640W30BD70A MM#862859FLASH 28F64 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。