參數(shù)資料
型號: PH28F640L18B85
廠商: INTEL CORP
元件分類: PROM
英文描述: StrataFlash Wireless Memory
中文描述: 4M X 16 FLASH 1.8V PROM, 85 ns, PBGA56
封裝: 0.75 MM PITCH, LEAD FREE, VFBGA-56
文件頁數(shù): 33/106頁
文件大小: 1272K
代理商: PH28F640L18B85
Intel StrataFlash Wireless Memory (L18)
Datasheet
Intel StrataFlash Wireless Memory (L18)
Order Number: 251902, Revision: 009
April 2005
33
Note:
WAIT shown deasserted during asynchronous read mode (RCR[10]=0 Wait asserted low).
R311
R312
t
CHVL
t
CHTX
CLK Valid to ADV# Setup
WAIT Hold from CLK
0
3
-
-
ns
ns
1
1,5
NOTES:
1.
See
Figure 8, “AC Input/Output Reference Waveform” on page 28
for timing measurements and max allowable input slew
rate.
OE# may be delayed by up to t
ELQV
– t
GLQV
after CE#’s falling edge without impact to t
ELQV
.
Sampled, not 100% tested.
Address hold in synchronous burst mode is t
or t
VHAX
, whichever timing specification is satisfied first.
Applies only to subsequent synchronous reads.
The specifications in
Section 7.3
will
only
be used by customers (1) who desire a 1.35 to 2.0 V
operating range OR
(2) who desire to transition their host controller from a 1.7 V to 2.0 V V
CCQ
voltage now to a lower range in the future.
2.
3.
4.
5.
6.
Num
Symbol
Parameter
Speed
–85
Units
Notes
Min
Max
Figure 11.
Asynchronous Single-Word Read with ADV# Low
R5
R7
R6
R17
R15
R9
R4
R8
R3
R1
R2
Address [A]
ADV#
CE# [E}
OE# [G]
WAIT [T]
Data [D/Q]
RST# [P]
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