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SBOS292A DECEMBER 2003 REVISED AUGUST 2004
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16
flag is programmed for high, then > 97% ADC range will
be a fault; if programmed for low, then < 3% ADC range
will be a fault. In this configuration, the system software
can be used to distinguish between over- or
under-pressure
condition,
out-of-control process, or a sensor fault.
which
indicates
an
POWER-UP AND NORMAL OPERATION
The PGA309 has circuitry to detect when the power
supply is applied to the PGA309, and reset the internal
registers and circuitry to an initial state. This reset also
occurs when the supply is detected to be invalid, so that
the PGA309 is in a known state when the supply
becomes valid again. The rising threshold for this circuit
is typically 2.2V and the falling threshold is typically
1.7V. After the power supply becomes valid, the
PGA309 waits for approximately 25ms and then
attempts to read the configuration data from the
external EEPROM device.
If the EEPROM has the proper flag set in address
locations 0 and 1, then the PGA309 continues reading
the first part of the EEPROM; otherwise, the PGA309
waits for one second before trying again. If the PGA309
detects no response from the EEPROM, the PGA309
waits for one second and tries again; otherwise, the
PGA309 tries to free the bus and waits for 25ms before
trying to read the EEPROM again. If a successful read
of the first part of the EEPROM is accomplished,
(including valid Checksum1 data), the PGA309 triggers
the Temp ADC to measure temperature. For 16-bit
resolution results, the converter takes approximately
125ms to complete a conversion. Once the conversion
is complete, the PGA309 begins reading the Lookup
Table information from the EEPROM (second part) to
calculate the settings for the Gain DAC and Zero DAC.
The PGA309 reads the entire Lookup Table so that it
can determine if the checksum for the Lookup Table
(Checksum2) is correct. Each entry in the Lookup Table
requires approximately 500
μ
s to read from the
EEPROM. Once the checksum is determined to be
valid, the calculated values for the Gain and Zero DACs
are updated into their respective registers, and the
output amplifier is enabled. The PGA309 then begins
looping through this entire procedure, starting with
reading the EEPROM configuration registers from the
first part of the EEPROM, then starting a new
conversion on the Temp ADC, which then triggers
reading the Lookup Table data from the second part of
the EEPROM. This loop continues indefinitely.
DIGITAL INTERFACE
There are two digital interfaces on the PGA309. The
PRG pin uses a One-Wire, UART-compatible interface
with bit rates from 4.8Kbits/s to 38.4Kbits/s. The SDA
and SCL pins together form an industry standard
Two-Wire interface at clock rates from 1kHz to 400kHz.
The external EEPROM uses the Two-Wire interface.
Communication to the PGA309 internal registers, as
well as to the external EEPROM, for programming and
readback can be conducted through either digital
interface.
It is also possible to connect the One-Wire
communication pin, PRG, to the V
OUT
pin in true
three-wire sensor modules and still allow for
programming. In this mode, the PGA309 output
amplifier may be enabled for a set time period and then
disabled again to allow sharing of the PRG pin with the
V
OUT
connection. This allows for both digital calibration
and analog readback during sensor calibration in a
three-wire sensor module.
The Two-Wire interface has timeout mechanisms to
prevent bus lockup from occurring. The Two-Wire
master controller in the PGA309 has a mode that
attempts to free up a stuck-at-zero SDA line by issuing
SCL pulses, even when the bus is not indicated as idle
after a timeout period has expired. The timeout will only
apply when the master portion of the PGA309 is
attempting to initiate a Two-Wire communication.