參數(shù)資料
型號(hào)： PF38F3352LLZDQ0
廠商： INTEL CORP
元件分類： 存儲(chǔ)器
英文描述： SPECIALTY MEMORY CIRCUIT, PBGA88
封裝： 11 X 13 MM, SCSP-88
文件頁(yè)數(shù)： 52/54頁(yè)
文件大?。?/td> 966K
代理商： PF38F3352LLZDQ0
768-Mbit LVQ Family with Asynchronous Static RAM
Datasheet
7
1.2
Acronyms
Buffered-EFP
Buffered Enhanced Factory Programming
CUI
Command User Interface
OTP
One-Time Programmable
PLR
Protection Lock Register
PR
Protection Register
RCR
Read Configuration Register
RFU
Reserved for Future Use (all unused active signals in a package ballout)
SR
Status Register
WSM
Write State Machine
APS
Automatic Power Savings
CFI
Common Flash Interface
MLC technology
Multi-Level-Cell technology
RWE
Read-While-Erase
RWW
Read-While-Write
1.3
Conventions
VCC
Signal or voltage connection
VCC
Signal or voltage level
Set
Logical one (1)
Clear
Logical zero (0)
0x
Hexadecimal number prefix
0b
Binary number prefix
SR[4]
Denotes an individual flash status register bit, in this case bit 5 of
SR[7:0].
D[15:0]
Denotes a group of similarly named signals, such as data bus.
A5
Denotes one element of a signal group membership, in this case address
bit 5.
F[3:1]-CE#, F[2:1]-OE# This is the method used to refer to more than one chip-enable or output
enable at the same time. When each is referred to individually, the
reference will be F1-CE# and F1-OE# (for die #1), F2-CE# and F2-OE#
(for die #2), and F3-CE# and F3-OE#(for die #3). “F” denotes the flash
specific signal and “CE#” is the root signal name of the flash die. Other
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