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參數(shù)資料
| 型號： | PF38F3352LLZDQ0 |
| 廠商： | INTEL CORP |
| 元件分類： | 存儲器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA88 |
| 封裝： | 11 X 13 MM, SCSP-88 |
| 文件頁數(shù)： | 42/54頁 |
| 文件大?。?/td> | 966K |
| 代理商： | PF38F3352LLZDQ0 |
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768-Mbit LVQ Family with Asynchronous Static RAM
Datasheet
47
NOTE:
xxH=0x04, 0x05, 0x06 or 0x07
18.2.2
Cautions for Setting PSRAM Mode Register
For the PSRAM Mode Register setting, the internal counter status is judged by toggling P-CS# and
R-OE#. Therefore, toggle P-CS# at every cycle during entry (read cycle twice, write cycle twice),
and toggle R-OE# like P-CS# at the first and second read cycles. If incorrect addresses or data are
written, or are written in an incorrect order, the setting of the PSRAM Mode Register will be set
incorrectly.
When the highest address is read consecutively three or more times, the Mode Register setting
entries are not performed correctly.
Note:
Immediately after the highest address is read, the setting of the Mode Register is not performed
correctly.
Perform the setting of the Mode Register after power application or after accessing other than the
highest address.
Once the refresh density has been set in the Mode Register, the setting is retained until it is reset
again while power is continuously applied. However, the Mode Register setting becomes
undefined if the power is turned off. The Mode Register must be reset after after any power cycle.
Figure 21. PSRAM Mode Register Setting Flowchart
Data=00H
Write to Highest Address
Data=xxH
Begin Normal
Operation
Read Highest Address
by Toggling both P-CS#
and R-OE#
START
Write to Highest Address
Read Highest Address
by Toggling both P-CS#
and R-OE#
Fail
Mode Register
setting exit
No
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