參數(shù)資料
型號(hào)： pentium II cpu
廠商： Intel Corp.
英文描述： Pentium II Processor AT 450MHZ(工作頻率450兆赫茲奔II處理器)
中文描述： 奔騰II處理器在450MHz（工作頻率450兆赫茲奔二處理器）
文件頁(yè)數(shù)： 25/84頁(yè)
文件大小： 1092K
代理商： PENTIUM II CPU
Pentium
II Processor at 350 MHz, 400 MHz, and 450 MHz
Datasheet
25
intrinsic trace capacitance for the AGTL+ signal group traces is known and well-controlled. For
more details on GTL+, see the
Pentium
II Processor Developer's Manual
(Order Number
243502) and AP-827,
100 MHz GTL+ Layout Guidelines for the Pentium
II Processor and Intel
440BX AGPset
(Order Number 243735).
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium
II processor frequencies and cache sizes.
2. Pentium II processors contain AGTL+ termination resistors at the end of each signal trace on the processor substrate.
Pentium II processors generate V
REF
on the processor substrate by using a voltage divider on V
TT
supplied through the
SC 242 connector.
3. V
TT
must be held to 1.5 V ±9%; dI
CC
VTT
/dt is specified in
Table 5
. It is recommended that V
TT
be held to
1.5 V ±3% while the Pentium II processor system bus is idle. This is measured at the processor edge fingers.
4. V
REF
is generated on the processor substrate to be 2/3 V
TT
nominally.
2.13
System Bus AC Specifications
The Pentium II processor system bus timings specified in this section are defined at the Pentium II
processor edge fingers and the processor core pads. Unless otherwise specified, timings are tested
at the processor core during manufacturing. Timings at the processor edge fingers are specified by
design characterization. See
Section 7.0
for the Pentium II processor edge connector signal
definitions. See the
Pentium
II Processor at 233, 266, 300, and 333 MHz
(Order Number 243335)
for more detail.
Table 9
through
Table 20
list the AC specifications associated with the Pentium II processor system
bus. These specifications are broken into the following categories:
Table 9
through
Table 11
contain the system bus clock core frequency and cache bus frequencies,
Table 12
and
Table 13
contain the AGTL+ specifications,
Table 14
and
Table 15
are the CMOS signal group
specifications,
Table 16
contains timings for the Reset conditions,
Table 17
and
Table 18
cover
APIC bus timing, and
Table 19
and
Table 20
cover TAP timing. For each pair of tables, the first
table contains timing specifications for measurement or simulation at the processor edge fingers.
The second table contains specifications for simulation at the processor core pads.
All Pentium II processor system bus AC specifications for the AGTL+ signal group are relative to
the rising edge of the BCLK input. All AGTL+ timings are referenced to V
REF
for both ‘0’ and ‘1’
logic levels unless otherwise specified.
The timings specified in this section should be used in conjunction with the I/O buffer models
provided by Intel. These I/O buffer models, which include package information, are available for
the Pentium II processor in Quad format as the
Pentium
II Processor I/O Buffer Models
, Quad
Format (Electronic Form) on Intel’s website: “http://www.intel.com.” GTL+ layout guidelines are
also available in AP-827,
100 MHz GTL+ Layout Guidelines for the Pentium
II Processor and
Intel
440BX AGPset
(Order Number 243735).
Care should be taken to read all notes associated with a particular timing parameter.
Table 8.
AGTL+ Bus Specifications
1, 2
Symbol
Parameter
Min
Typ
Max
Units
Notes
V
TT
Bus Termination Voltage
1.365
1.50
1.635
V
V
1.5 V ±9%
3
R
TT
Termination Resistor
56
±5%
V
REF
Bus Reference Voltage
2/3 V
TT
4
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